anilinintel
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Re: Quartus prime pro 20.3 installation failure on windows machine?
hi, No hurry. please try to give the solution to the Original Post. Multiple file download of 12 GB .tar file is heavy for me. If its not too big for you. please download and cross verify the part2 file format. But I'm sure that the same error may encounter for this approach as well.6.1KViews0likes1CommentRe: Quartus prime pro 20.3 installation failure on windows machine?
Hi, I also got the same thought of renaming .qdz to .exe on that day itself. But the same error repeated again. I am familiar that windows installer should be .exe and altera device support comes with .qdz format.6.1KViews0likes3CommentsQuartus prime pro 20.3 installation failure on windows machine?
Hello, I downloaded required setup files suitable for a windows machine to install Quartus prime PRO 20.3 latest version. Because of heavy setup files sizes. I decided to download setup files part by part from an "individual files" tab from this link. https://fpgasoftware.intel.com/ This way I downloaded all 4 links to get these files listed below. And one more extra link to support devices. 1. QuartusProSetup-20.3.0.158-windows.exe 2. quartus_part2-20.3.0.158_2.qdz 3. ModelSimProSetup-20.3.0.158-windows.exe 4.ModelSimProSetup-part2-20.3.0.158-windows.exe 5. diamondmesa-20.3.0.158.qdz when I try to install by double-clicking on the main setup file i.e (QuartusProSetup-20.3.0.158-windows.exe). I encountered a small window saying. "this installation can't find Quartus prime part2 package". the fact is this part2 package available in the same folder sitting along with main setup files. I can show my screenshot as an attachment. where one can see all files available in the picture and the error message. someone, please help me to proceed further.Solved6.2KViews0likes10CommentsRe: How to reduce re-compilation time in Quartus pro ?
Hi, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an899.pdf In this pdf mentioned above. there was a link for tutorial on page no 5. which is unable to download and use. please look into that https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an899_fast_preservation_tutorial_files_193.zip sometimes download drops immediately and sometimes even wont starts. Regards, Anil1KViews0likes0CommentsRe: Quartus prime ver 20.1's Nios sbt not working
Hi, From the link, you posted in the last reply. you can browse into "Installation FAQ". there it mentioned what to do. "Is the Nios® II Software Build Tools (SBT) for Eclipse included in the full installation of the Intel® Quartus® Prime Pro Edition software starting from version 19.1?". https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/why-does-the-nios--ii-not-installed-after-full-installation-of-t.html follow this link and steps. Regards, Anil2.8KViews0likes3CommentsHow to reduce re-compilation time in Quartus pro ?
Hello, We do a lot of stuff in platform designer connecting so many complex custom ips and Altera IP's together and finally do compilation which will take over a 16 hrs - 24 hrs to generate .sof file. It's not a problem at least for the first time. But if we make a small change in our custom RTL at least a single line of code. Again it takes 16hrs/24 hrs compilation time. we don't want this to happen again here for re-compilation in which all other IPS are not touched or not modified. Is there a way or suggest me the technique so that it wont take huge compilation time for every run for minor modifications. Regards, Anil1.1KViews0likes3CommentsRe: Expoting Signal Tap waveform data with a format .csv
Hello, My multi_bit signals are displaying as multi_bit only in signal tap. I can verify my waveform data by zooming in and zooming out on signal tap GUI and verified hex data. but I cant do this for a 100's of clock data. for this reason I tried exporting to .csv format . but there everything shown in single bit. In breif In verilog RTL : my concerned bus is : reg [255:0] km_bus; In SignalTap Gui: I selected and added this 256 bus into my signal tap window and went for compilation. After compilation , programming and after met trigger condition, my 256 bus stayed as 256 bus only. no issues here. i can see my hex data directly and verified. In .csv exported file: I see km_bus[0],km_bus[1],km_bus[2].....km_bus[255] mentioned column wise in different excel cells. Irrelevant to this post. but i want to mention here. I exported .vcd file and converted to .wlf file with modelsim and read by modelsim. In vsim wavewindow all bus bits are collapsed(bit blasted). Its really difficult to combine those and look for hex data. And in Excel i dont know how to merge cells to get hex data.3.4KViews0likes1CommentExpoting Signal Tap waveform data with a format .csv
Hi, I have a large data on signal tap currently displaying on Quartus pro "signal tap logic analyzer" gui window. I want that waveform data to be verified on some other tool like excel. I do exporting this data with a .csv format with a clock period of 1 sec. As expected a file stp1.csv was exported into my directory. I opened this .csv file with an excel tool. but my problem became more complex because of data shown in bit blasting . like I have a data bus of 256 bit wide (reg [255:0] bus) shown separately as bus[0],bus[1]...so on bus[255] in different excel cells. so, question is how easily i can crosscheck my results, i want every bus to be preserved together without bit blasting. or anyother method or settings change needed to accomplish what am i looking for ? Regards, Anil3.5KViews0likes3Comments