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Re: CPLD Date Code
Hi amirborna, the desired information can be find in the following web pages: date code decoder: https://www.intel.com/content/www/us/en/programmable/support/quality-and-reliability/decoder.html top side marking format: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10292013_192.html Regards, Martin1.4KViews0likes0CommentsRe: About the ground pad of E144-pin package
Hi Ysuzu21, there is the following sentence in a pinout document for Intel MAX 10 device, 10M16SA (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/10m16sa.pdf😞 The E144-pin package has an exposed ground pad at the bottom of the package. The exposed ground pad is used for electrical connectivity and not for thermal purposes. You must connect the exposed ground pad to the ground plane of the PCB. Regards, Martin1.7KViews0likes0CommentsRe: MAX+plus II error
Hi Paulo, EPM7064 and EPM7064S devices have the same gates count, macrocells count, maximum user I/O pins and device pinout. But there is JTAG interface available for MAX 7000S only. When the JTAG interface in MAX 7000S devices is used for in-system programming, four I/O pins become JTAG pins. What is the JTAG interface settings in MAX+PLUS II? Regards, Martin908Views0likes0CommentsRe: Pin "K3" of FPGA "10M25DAF484"
Hi Nakamura_kimi, I would recommend to look to the similar thread: Will the 5CEFA4U19 chip work without some power pins connected as suggested by the Quartus migration feature. I would recommend to look to Intel MAX 10 FPGA Device Family Pin Connection Guidelines (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf). There is the following fragment as an explanation of NC pin, section Reference Pins, p.12: Pin Name = NC, Pin Type = No Connect, Pin Description = Do not drive signals into these pins. Connection Guidelines = When designing for device migration, these pins may be connected to power, GND, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern, leave these pins floating. Regards, Martin2.2KViews0likes3CommentsRe: Cyclone V Logic Elements
Hello Bill, I assume the article FPGAs: System gates or logic cells/elements? can be helpful: www.eetimes.com/fpgas-system-gates-or-logic-cells-elements A fragment from the mentioned article: "Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates." I would recommend to try to implement your project in the Quartus design system for Intel/Altera Cyclone V family. This device family is supported via free Intel Quartus Prime Lite Edition. (https://fpgasoftware.intel.com/?edition=lite). Regards, Martin1.8KViews1like3CommentsRe: 10M16DCU324 power up sequence
Hi XShen1, according to the following document: Intel® MAX® 10 Power Management User Guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pdf😞 The Intel MAX 10 device supports any power-up or power-down sequence to simplify system-level design. Regards, Martin1.7KViews0likes0CommentsRe: CPLD Max V equivalent gates
Hello Neha, I assume the article FPGAs: System gates or logic cells/elements? can be helpful: www.eetimes.com/fpgas-system-gates-or-logic-cells-elements A fragment from the mentioned article: "Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates." I would recommend to try to implement your project in the Quartus design system for Intel/Altera MAX V family. This device family is supported via free Intel Quartus Prime Lite Edition. (https://fpgasoftware.intel.com/?edition=lite). According to my experiences with CPLD devices it is more important to have enough flip-flops. But it depends on the current project of course. Regards, Martin1.7KViews0likes1CommentRe: Programming a MAX 10 from a MCU using JTAG
Hello Pastel, the following web page and documents can be helpful: - https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/programming/jam.html - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an425.pdf Regards, Martin1.8KViews0likes0Comments