PalmPlumb
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Re: Unable to simulate DDR3 controller
Hi Adzim, Thank you for the detailed explanation. It makes sense that the invalid Platform Designer file error occurs due to the absence of a .qsys file. The workaround to locate the design file via right-click is helpful. For the simulation steps, I’ll try following your instructions with Questasim and see if the "do run.do" command works as expected. The reference link should also be useful for further clarification. Appreciate your assistance!719Views0likes0CommentsRe: Agilex® 7 P-Tile Multi-Channel DMA Debug Toolkit isn't working in Quartus® v22.4
Thank you for sharing this issue. It seems the Agilent P-tile MCDMA PCIe Debug Toolkit is encountering a timeout error with Gen4 x8 in Quartus v22.4, though it works fine for Gen4 x16. Since this is planned to be fixed in a future Quartus Pro release, you might want to keep an eye on updates from Intel. The provided link to the Multi Channel DMA Intel FPGA IP for PCI Express User Guide could also offer additional insights or workarounds in the meantime.4.8KViews0likes2Comments