justin-rosner
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Re: Intel HLS pipeline::lsu won't dispatch more than 8 request
Hi @AUT , Unfortunately at this time, without specifically modifying the generated Verilog (i.e. updating the KERNEL_SIDE_MEM_LATENCY so that the instantiated FIFO is larger), there is no way to increase the capacity of the FIFO associated with the pipelined LSU. What is the desired number of dispatch requests that you are trying to achieve?1.9KViews0likes1Comment