ContributionsMost RecentMost LikesSolutionsClarification on rx_st_empty Behavior for Unaligned Transfers (1 DWORD Length) in P-TILE :- I have a few doubts regarding how the rx_st_empty signal is updated during unaligned transfers where the SOP and EOP are asserted in the same cycle, specifically for a length of 1 DWORD. For a write request with aligned address (e.g., address = 0), the valid data is located in rx_st_tdata[31:0], and the remaining bytes [255:32] are empty , leading to rx_st_empty = 7 (as only 1 DWORD is valid). What happens if the address is unaligned (e.g., address = 4)? The valid DWORD shifts to rx_st_tdata[63:32]. In this case: Will rx_st_empty still update to 7 as before, considering the higher bits [255:64] and [31 : 0] are invalid? Or will it update to 6 since only [255:64] are empty? For other unaligned addresses (e.g., address = 8, C, 10, ..., 1C), where the valid DWORD keeps shifting to the right, how does rx_st_empty update in these cases Especially for .1 dword length case ? For a read request of 1 DWORD length, does rx_st_empty behave similarly to a write request with unaligned addresses, or is its value fixed regardless of alignment? I’d appreciate any insights or examples to clarify how rx_st_empty behaves in such scenarios. Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi Winicent, After configuring the P-Tile as a Native Endpoint IP and providing all the necessary settings in the GUI, if we program it onto the Stratix 10 board, will the enumeration take place? How can we verify if the enumeration was successful? We are using a Stratix 10 board with Quartus version 20.3. Which signals, such as ninit_done, ref_clk[1:0], and reset, need to be connected for the P-Tile IP? Is there a user guide that explicitly outlines these requirements? Regards Thanavignesh Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi wincent, Could you clarify the exact simulation time in hours when running in VCS ? The device we are using is a Stratix 10, specifically 1SD110PJ2F43E2VG. We have also tested on other boards supporting P-Tile, and the results show similar simulation times in quest sim . Could you share your experimental results for comparison in questa sim? Regards, Thana Vignesh Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi wincent, ->Were any signals added before ld_debug? No, signals were added only after ld_debug and before run -all in the waveform window. ->When the simulation succeeds, are any signals triggered? Did you set any trigger conditions in the testbench? No, there are no signals triggered. No, the testbench remains unchanged and is the default one generated with the P-TILe example design BFM model only configured as 4x8. ->Is there a specific signal you need to monitor? No specific signals are being monitored . The goal is to run the simulation faster to integrate and verify our user logic along with the BFM. ->Could VCS be used as an alternative simulator for faster simulation? Unfortunately, only Aldec and Questa Sim are available, and both exhibit similar simulation times. 1.Is there a way to log signals into the .wlf file without adding/logging them to the waveform window? Is there anything that need to change in script? 2.We suspect that the p0_reset_status_n signal is delayed in our environment, as it is asserted only after 100,000 ns. Could you please check in your environment when this signal is asserted for both the Root Port (RP) and Endpoint (EP) and when was the link training initiated ? Additionally, please attach a snapshot showing the assertion timing. Note: The P-Tile example design was generated with the configuration modified to Gen 4x8, while all other settings were left unchanged which was generated in Quartus v23.3. Regards Thanavignesh Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi Wincent, Are there any specific system requirements, such as having 100GB of RAM, to achieve faster simulation performance for the P-Tile example design in Questa Sim? Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi Wincent, With the default settings and only the change to Gen 4x8 configuration, it takes around 8 hours to complete without any signals logged. To debug this further, could we arrange a call to discuss the issue in detail? I can share the .ip file and any other necessary files during the call for better clarity. Please let me know a convenient time, and I’ll make the arrangements. Regards, Thanavignesh Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi wincent, 1.In the provided snippet from the Endpoint, the ref_clk0/1 and coreclkout_hip signals appear to be functioning correctly, and the pin_perst_n along with other reset signals asserted as expected during initialization. However, the p0_reset_status_n signal, an output of the PCIe Hard IP core, remains deasserted, and we lack visibility into the internal logic driving this signal. Are there alternative methods to control or debug the behavior of the reset_status signal? 2.Additionally, what is the typical simulation runtime for the P-Tile example design configured for 4x8 operation with default settings when using Questa 23.4 or other supported versions? Regards, Thanavignesh Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi wincent, 1.Is there any specific reason you need to know what happen ? Yes Understanding from Link Training and Process Flow Can you explain how the process starts for link training in the code and how and where the subsequent tasks are called in the BFM for both the Root Port (RP) and Endpoint (EP)? I’d like to understand how the process begins and progresses 2.When using the option set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" in msim_setup.tcl: If I run ld_debug and run -all, it takes 4.5 hours to reach the log message: INFO: 126725 ns RP User Avmm Driver: begin RP Configuration, and the simulation finishes after 4.5 hours. If I use ld and run -all, it takes 40 minutes to reach the same message INFO: 126725 ns RP User Avmm Driver: begin RP Configuration, but the simulation seems to get stuck afterward with no further logs waiting for the wait_request signal to deassert from the Root Port BFM.. What could be causing these differences, and how can I ensure smooth simulation without getting stuck? 3.Warning About Optimizations When running msim_setup.tcl and ld_debug I get this warning: Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility. How can I avoid this warning while maintaining necessary visibility without impacting simulation performance? Could this warning be related to the delays I’m experiencing? 4. Reset_status_n Signal Delay In the simulation waveform ,One observation is the p0_reset_status_n signal remains low for approximately 100,000 ns, which seems to delay progress. Are there any adjustments or optimizations to reduce this reset assertion time? Could this be the case delay I’m experiencing? Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi Wincent, I simulated the example design generated in Quartus 23.3 using Questa Intel FPGA version 23.2. It took approximately 4.5 hours to reach the first log info: INFO: 126725 ns RP User Avmm Driver: begin RP Configuration. The simulation completed successfully after about 9 hours, with the final log : INFO: 242847 ns PIO ED MWr/Mrd Completed. SUCCESS: Simulation stopped due to successful completion. Is there any way to reduce the overall simulation time? What processes are running in the background before the 126725 ns mark? Is there any documentation available that explains the activities happening during this period? Re: Issue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design Hi Wincent, Thank you for your prompt response and for providing the workaround. I appreciate your help. I am currently using Questasim version 22.4. I applied the suggested solution with the command set USER_DEFINED_ELAB_OPTIONS "-voptargs=-noprotectopt" in Questsim 22.1, and the simulation completed successfully. Thanks also for sharing the reference link