aidab
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Re: how to simulate an example design PCIe in Questa 23.2
Hello VenTingT_Intel, Thank you for your response. I'm working on Agilex 7: AGIB027R29A1E2VR0. I hope this information is helpful. I'm currently attempting to simulate, but I'm encountering issues in Questa, such as insufficient sources, etc. I'm looking forward to your response. Thanks, Best Regards, Aida1.5KViews0likes0Commentshow to simulate an example design PCIe in Questa 23.2
Hello Intel community, I hope this message finds you well. I am reaching out for assistance in simulating the PCIe IP using the example design generated in Quartus with Questa software version 23.2. My goal is to simulate the example design using a PCIe Gen3 configuration. However, I am encountering issues during the simulation, and I am unsure about the specific Verilog files needed for simulation in Questa. Additionally, I'm trying to send data from the root point to the end point while visualizing the control signals of the IP in Gen3. Could you please guide me on the best approach for simulating the PCIe IP in Gen3 with Questa 23.2? Could you inform me about the specific Verilog files from the example design that I should use for simulation? I appreciate your assistance in advance. Best regards, Aida1.7KViews0likes7Comments