verilog
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Same file name with different content of two custom IP core. is it possible to compile it without error? How to separate compilation library for the files having the same name in QSYS?
we have designed our IP core files in such a way to comply a standard file name, so all custom IP has the common file name but with different content for each IP. Now when we try to accommodate more than one custom IP in QSYS having same file names Quartus gives compilation error: Error (10149): Verilog HDL Declaration error at "file_name".sv(62): identifier "file_name" is already declared in the present scope. Means Quartus found two files with the same name from QIP. so please suggest what would be the possible solution for the same. NOTE: we have so many numbers of IP core already design with same file names so no scope for rename it all.2.7KViews0likes2Comments