hburd
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HLS compiler not generating IP components
I'm trying to build the example projects that come with the HLS compiler. When I build for the FPGA (e.g. running the makefile in the "counter" example), the compiler runs without indicating any errors, but I don't find a *.ip file in the output directory like I expected. As far as I understand, I need this file to be able to load the component into Quartus (as implied by these steps and this video). This is the output when running the compiler. HLS$ i++ -march=CycloneV --simulator none counter.cpp -v Target FPGA part name: 5CGXFC7C7F23C8 Target FPGA family name: CycloneV Target FPGA speed grade: -8 Analyzing counter.cpp for hardware generation Verifying version information in the included files. Expecting version 22.3.0.116.1 for all included files. Included files passed version check. Checked: none. Optimizing component(s) and generating Verilog files Multiple files are present in the output directory (including a subdirectory called "ip") but not the ip component: HLS$ ls a.prj/components/count/ count_inst.v count_internal_hw.tcl count_internal.v count.qsys interface_structs.v ip linux64 I've installed the HLS compiler using the instructions here , since I need Cyclone V support. Any help would be greatly appreciated. Cheers870Views0likes4Comments