Benedict_Goh
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STRATIX10 Maximum Pressure
Hi, I would like to apply a Thermal Interface Material (TIM) to contact the STRATIX10 chip and a heatsink and I have a few questions: 1. What is the maximum pressure that can be applied to the top side of the STRATIX10 chip without causing any damage or performance degradation? 2. Is the maximum pressure the same for all variants of the STRATIX10 chip? Thank you!Intel Stratix10 Thermal Modelling using CTM
Hi, I have previously gotten the stratix10 CTM for solidworks from Intel. However, I am having some difficulties with the thermal modelling using the CTM. Questions as follow: For the Compact Thermal Model (CTM), I noticed that there is a gap between the substrate and sealant layers. Is this correct? (not sure if it is alright for me to share a screenshot of the CTM here showing this gap) To conduct a thermal analysis using the CTM, do I only input the thermal conductivity for the various items and their respective heat loads extracted from the EPE? Is this understanding correct? To evaluate the junction temperatures of the dies, we first evaluate the case temperature of the IHS from thermal simulation. Then, we use this formula T J = T CASE + TTDP * PSI JC (where TTDP and ψ JC values can be extracted from the EPE) to determine its junction temperature Do I need to input the ψ JC values extracted from the EPE for the respective dies in the thermal simulation? Which part of the die should the respective heat loads be applied? I am getting a negative ψ JC value from the EPE (HSSI_2_1). I would like to check what inputs may result in this? I am having some difficulties in identifying the thermal conductivities for the various parts in the CTM. The list provided in the PDF documents does not seem to tally with the file names in the CTM. Are you able to provide me with some clarity? (also not sure if I am able to attach a screenshot showing the names from the material list in the PDF and the file names of the various parts in the CTM) Thank you!
