Hieu007
New ContributorJoined 4 years ago
User Profile
New Contributor
User Widgets
Contributions
(vcom-1576) expecting ')'
Hey all, I've googled this problem and it always seems to be a missing semicolon or paren somewhere, but I've looked over my code and I see nothing. I know it's going to be simple and I will feel stupid, but I am just learning VHDL and going by the book. What is wrong with my signal declaration here? ** Error: D:/tkhts2/hieu007.vhd(15): near "orsum": (vcom-1576) expecting ')'. LIBRARY ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity BCD_Adder is Port ( x,y :in std_logic_vector(3 downto 0); S :out std_logic_vector(4 downto 0) ); End BCD_Adder; architecture Behavioral of BCD_Adder is Signal adjust :std_logic; Signal sum :std_logic_vector ( 4 downto 0); begin Sum <= ('0' & x)+y; Adjust<='1'when((sum > 9) orsum(4)='l') else '0'; S <= sum when (adjust ='0') else Sum + 6; end Behavioral;3.9KViews0likes3Comments