Jatin_Kumar
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Re: aoc command crashing with -profile switch
Hi BB, We are not running on DevCloud. We are trying to develop an IP for which we are using the FPGA for testing purpose. We have not run simulation yet. We have verified the design on emulator, and now trying to implement on FPGA with profiling. the aoc compiler works perfectly fine without the -profile switch, but when we enable the switch, I keep on getting the above crash dump, even for small design. Regards, Jatin897Views0likes0Commentsaoc command crashing with -profile switch
Crash dump: aoc: Warning: no argument provided for the option -profile, will enable profiling for all kernels by default aoc: Environment checks completed successfully. Quartus location: /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/quartus/bin/quartus_sh aoc: Cached files in /var/tmp/aocl/ may be used to reduce compilation time You are now compiling the full flow!! aoc: Selected target board package /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/board/s10mx_ref aoc: Selected target board s10mx_hbm aoc: Running OpenCL parser.... aoc: OpenCL parser completed aoc: Linking Object files.... aoc: Optimizing and doing static analysis of code... aoc: Linking with IP library ... aocl-llc: /nfs/sc/disks/swip_hld_1/ops/SC/hld/nightly/21.1/173.3/l64/p4/acl/llvm-project/llvm/include/llvm/Support/Casting.h:287: std::enable_if_t<(! llvm::is_simple_type<Y>::value), typename llvm::cast_retty<X, const Y>::ret_type> llvm::cast_or_null(const Y&) [with X = llvm::DILocation; Y = llvm::TypedTrackingMDRef<llvm::MDNode>; std::enable_if_t<(! llvm::is_simple_type<Y>::value), typename llvm::cast_retty<X, const Y>::ret_type> = llvm::DILocation*]: Assertion `isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"' failed. PLEASE submit a bug report to https://software.intel.com/en-us/support/priority-support and include the crash backtrace. Stack dump: 0. Program arguments: /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/aocl-bin/aocl-llc -march=fpga -board /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/board/s10mx_ref/hardware/s10mx_hbm/board_spec.xml -profile all -pass-remarks-input=pass-remarks.yaml -dbg-info-enabled --dependendency-list-file=temp_dependencies_list.txt.temp simram.bc -o simram.v 1. Running pass 'Unnamed pass: implement Pass::getPassName()' on module 'simram.bc'. /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(_ZN4llvm3sys15PrintStackTraceERNS_11raw_ostreamE+0x2a)[0x7ffff1f270ba] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(_ZN4llvm3sys17RunSignalHandlersEv+0x34)[0x7ffff1f24bb4] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0xe7fd03)[0x7ffff1f24d03] /lib64/noelision/libpthread.so.0(+0x10bd0)[0x7ffff0e98bd0] /lib64/libc.so.6(gsignal+0x37)[0x7ffff0281f67] /lib64/libc.so.6(abort+0x13a)[0x7ffff028333a] /lib64/libc.so.6(+0x2dd66)[0x7ffff027ad66] /lib64/libc.so.6(+0x2de12)[0x7ffff027ae12] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0xf4f9b5)[0x7ffff1ff49b5] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3ec0bca)[0x7ffff4f65bca] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3e66fe2)[0x7ffff4f0bfe2] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x414a547)[0x7ffff51ef547] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x414a870)[0x7ffff51ef870] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x414ab7e)[0x7ffff51efb7e] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3e6eee0)[0x7ffff4f13ee0] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3dcb279)[0x7ffff4e70279] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3dcef27)[0x7ffff4e73f27] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3dd0282)[0x7ffff4e75282] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x3dd3fff)[0x7ffff4e78fff] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(+0x2835671)[0x7ffff38da671] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(_ZN3acl25GriffinPipelineLegacyPass11runOnModuleERN4llvm6ModuleE+0xef2)[0x7ffff38dd612] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/bin/../lib/libLLVM-11git.so(_ZN4llvm6legacy15PassManagerImpl3runERNS_6ModuleE+0x412)[0x7ffff2087a42] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/aocl-bin/aocl-llc(+0x132a8)[0x5555555672a8] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/aocl-bin/aocl-llc(main+0x351)[0x55555555f211] /lib64/libc.so.6(__libc_start_main+0xf5)[0x7ffff026d725] /nfs/site/disks/rtl_ip_simram/tools/intelFPGA_pro/21.1/hld/llvm/aocl-bin/aocl-llc(_start+0x29)[0x55555555f569] Error: Verilog generator FAILED. Refer to simram/simram.log for details.925Views0likes2Comments