de10
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ALTLVDS_RX inclok pin. Dedicated clock port?
I'm designing an FPGA, using Enclustra Mercury PE1 and SA2. The FPGA is Cyclone V ST D6. I'm trying to assign the data entry and clock pins. Someone knows if it is possible to connect the inclock input to any differential I/O. Or do I have to use dedicated clock pins (clk[0..7])? Attach the image marking the pins dedicated to clk:
