SIGMOD/DaMoN 2020 Workshop on Data Management on New Hardware Keynote to Focus on Database Acceleration Through Coherent Attachment to Servers
José Roberto Alvarez, Senior Director and leader of the Technology and Innovation CTO Office at the Intel Programmable Solutions Group, will be giving the keynote speech at the 16th International Workshop on Data Management on New Hardware (DaMoN 2020) on Monday, June 15, 2020. His keynote title is “A Vision for Expandable Data Management Infrastructure and Acceleration with Heterogenous Configurable Systems.” Alvarez will discuss the ways that FPGAs can provide faster look-aside and inline acceleration for CPU/storage, CPU/memory, CPU/network, and network/storage paths through coherent attachment to server CPUs. Heterogenous compute systems centered around FPGAs can help data center architects meet TCO, performance, and power density goals. He will also discuss specific FPGA features including the Intel UPI and open CXL coherent interconnect protocols that expand and accelerate server access to DDR SDRAM, Intel® Optane™ persistent memory and persistent storage, and high-speed networks through Intel FPGAs. In addition to these device and platform features, Alvarez will discuss how software developers can use such platforms using Intel® OneAPI toolkits. The DaMoN Workshop is part of the SIGMOD/PODS conference. Registration for the DaMoN workshop is through the SIGMOD/PODS 2020 conference registration site. The event is virtual this year. For more information about the DaMoN Workshop, click here. To register, click here. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The Next Platform discusses Gen-Z coherent memory, UPI, and FPGAs for server architecture acceleration
Last November at Supercomputing ’19 (SC19), the Gen-Z Consortium booth contained a proof-of-concept (POC) SQLite database acceleration demo that showed a 5x performance improvement in the average database INSERT operation time, with a clear path to even better performance. (See “Gen-Z Consortium demos 5x SQLite database acceleration at SC'19 with an Intel UPI link between an Intel® Xeon CPU and an Intel® FPGA.”) That demo was based on an Intel® Xeon® CPU communicating with an Intel® FPGA configured over a coherent, low-latency Intel® Ultra Path Interconnect (UPI) link using an Intel UPI Home Agent IP block contributed by Intel specifically for this POC demo. The UPI IP block was connected to a Gen-Z controller IP block, also instantiated in the FPGA, which ultimately communicated with a Gen-Z Memory Module (ZMM). The Gen-Z controller IP was developed and provided by Intelliprop (an Intel® FPGA Partner Program member). Last week, the online tech site The Next Platform discussed this demo in an article written by Timothy Prickett Morgan titled “Gen-Z Memory Servers Loom On The Horizon.” The relevant part of the article states: “…the FPGA team at Intel worked with server makers HPE and Dell and chip designer IntelliProp to create a bridge from CPUs to remote Gen-Z ZMMs and compared the latency of a transaction processing benchmark on the SQLite database with the data being stored either on local NVM-Express drives on the server or on the remote Gen-Z memory. In this case, IntelliProp created a bridge from the [Intel] UltraPath Interconnect (UPI) NUMA links used on [Intel] ‘Skylake’ and ‘Cascade Lake’ processors to the Gen-Z protocol… The latency of database reads was 5X lower across the Gen-Z link to the ZMM than it was for locally attached NVM-Express drives.” Moving forward, this POC demo and the associated IP will migrate to the recently announced Intel® Stratix® 10 DX FPGA, which supports the Intel UPI protocol as well as PCIe Gen4 x16 with hardened IP. (See “Talk to PCIe Gen4 x16, Intel® UPI, Intel® Optane™ DC Persistent Memory, and SDRAM with one Intel® Stratix® 10 DX FPGA.”) Meanwhile, Intel and other industry leaders including Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, and Microsoft are developing a next-generation, coherent CPU interconnect called the Compute Express Link (CXL), which will be supported by the new Intel® Agilex™ FPGA family. (See “How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?”) If you are struggling to connect some of these coherent dots, The Next Platform will be holding a live event next week in San Jose on January 22 called The Next FPGA Platform. This event gathers together many preeminent industry leaders to bring you up-to-the-minute information about and deep, expert insights into FPGAs and FPGA acceleration in servers and datacenters. Intel is a Platinum sponsor for this event. Timothy Prickett Morgan, co-editor and co-founder of The Next Platform and author of the article discussed above, is one of the event’s hosts. For more information about The Next FPGA Platform event, see “FPGA Acceleration in the Datacenter: See and Hear High-Level Experts from Intel and FPGA Partners at The Next FPGA Platform Day-Long, Live Event – January 22 in San Jose” or click here for the event information page with a full agenda. Or, just click here to go ahead and register. Legal Notices and Disclaimers: Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Altera is a trademark of Intel Corporation or its subsidiaries. Cyclone is a trademark of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.