Free “Ask an Expert Webinar”: Debugging with Signal Tap for Intel® FPGAS, June 27th 2023
Are you curious about debugging with the Signal Tap logic analyzer and some of the new innovations such as Signal Preservation, Incremental Signal Tap compilation, and Simulator-Aware Signal Tap? Intel is holding an "Ask an Expert Webinar" on Tuesday, June 27 at 9:00 AM PDT to answer your questions about the Signal Tap logic analyzer and the latest innovations.
SAP accelerates compression workload in POC with Intel® OFS
A recent development project by developers demonstrates how easy it is to accelerate containerized workloads using an Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) and The project moved an FPGA-accelerated compression algorithm called Re-Pair into a container and made it available as a service to customers using SAP HANA, a relational database management system. This project serves as a proof of concept (PoC) and demonstrates that FPGA-accelerated application workloads like Re-Pair can easily migrate into the pervasive containerized environments used in modern data centers without significant porting effort or major challenges.
Transfer 2.4 Tbps (or 4.32 Tbps) with One Intel® Agilex™ FPGA
High-speed serial transceivers quickly became a foundational FPGA component when they appeared more than 20 years ago and have grown increasingly important as their bandwidth has exploded. Intel has just published a 5-minute video that demonstrates the Intel Agilex FPGA family’s high-speed data-transfer capabilities enabled by the F-tiles’ high-speed transceivers. The demo uses the Intel SuperLite IV IP...Video Demo: Designing Broadcast Video Equipment Using SDI
Intel has just published a video with an SDI demo implemented with an Intel Agilex I-Series FPGA and the SDI II IP core. The demo is based on an SDI retransmit design that does not require an external VCXO for genlocking purposes. Instead, it uses the Intel Agilex I-Series FPGA’s internal transmit phase-locked loop (PLL) on the FPGA’s F-tile in fractional mode.
ServeTheHome’s Editor in Chief Visits Intel Networking Lab and Groks FPGA-Based IPUs
Patrick Kennedy, Editor in Chief at ServeTheHome, has just published an in-depth, hands-on article and YouTube video about his recent Infrastructure Processing Unit (IPU) adventures at the Intel networking lab in Santa Clara, California. This was Patrick’s first hands-on experience with an FPGA-based IPU. The card that he worked with is a Silicom C5010X FPGA IPU, based on the Intel IPU C5000X-PL Platform.
