Why does the F-Tile Ethernet Dynamic Reconfiguration (DR) design not work when one of the profiles has PTP enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 23.3, the F-Tile Ethernet designs using Dynamic Reconfiguration with PTP enabled on some of the profiles will fail to work correctly if the startup profile of the design does not have PTP enabled. Resolution To work around this problem, ensure that the startup profile of your dynamically reconfigurable Ethernet design has PTP enabled if any of the profiles have PTP enabled.
Why does Quartus® Prime Pro Edition version 25.1.1 and later add a phased_clk_lock_interface conduit to the altera_eth_1588_tod IP when targeting Agilex® 7 FPGA devices?
Description In Quartus® Prime Pro Edition software version 25.1.1 and later, when targeting Agilex® 7 FPGA devices, the altera_eth_1588_tod IP exposes an additional phased_clk_lock_interface conduit. This interface conduit was not present in earlier Quartus® Prime Pro Edition versions. As a result, designs that were originally created and validated using Quartus® Prime Pro Edition version 25.1 or earlier may encounter connectivity issues or appear broken when migrated to newer software versions, due to the unexpected addition of this required conduit. Resolution To fix this problem in Quartus@ Prime Pro software version 25.3.1, install patch 1.23 below for the correct OS (Operating System) Readme: quartus-25.3.1-1.23-readme.txt Linux: quartus-25.3.1-1.23-linux.run Windows: quartus-25.3.1-1.23-windows.exe This problem is scheduled to be fixed in a future release of the Quartus@ Prime Pro Software.Which Protocols Support Spread Spectrum Clocking (SSC) in Agilex® 7 FPGA Devices?
Description In the Agilex® 7 FPGA device family, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using FGT transceivers in F-tile, SSC is enabled by selecting the “Enable Spread Spectrum Clocking” option, while keeping the “Enable TX FGT PLL fractional mode” option disabled in the F-Tile PMA/FEC Direct PHY IP. Resolution N/AWhy does Quartus® Prime Pro Edition report Critical Warning (22976) during the QTLG stage for F-Tile IPs not explicitly configured for Dynamic Reconfiguration when the F-Tile Dynamic Reconfiguration Suite IP is included in the same project?
Description In the Quartus® Prime Pro Edition software version 25.3.1, Critical Warning (22976) may be reported for non-Dynamic Reconfiguration F-Tile protocol IPs when they are instantiated in a design that also contains Dynamic Reconfiguration F-Tile IPs. This warning may appear even when Dynamic Reconfiguration is not required or intended for the non-DR F-Tile IPs. The warning message typically appears as follows: Critical Warning(22976): Dynamic Reconfiguration controller IP specification is missing for IP or IPs {IP_PATH}. Use IP_COLOCATE assignment to specify a Dynamic Reconfiguration controller IP. This warning does not affect design functionality or correctness. It is reported due to how Quartus® Prime Pro Edition software checks for Dynamic Reconfiguration controller assignments when both Dynamic Reconfiguration and non-Dynamic Reconfiguration F-Tile IPs are present in the same design. Resolution There is currently no workaround to suppress Critical Warning(22976) in the Quartus Prime Pro Edition software. If Dynamic Reconfiguration is not required for the IP reporting this warning, this warning can be safely ignored. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Warning(332158): Clock uncertainty characteristics of the Agilex™ 7 FPGA device family are preliminary
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may encounter this warning message during the Fitter stage when compiling designs targeting Agilex™ 7 FPGA devices. Although the release notes indicate the timing model is final, the warning message may still appear. Resolution After reviewing the release notes, confirming that the timing model for the Agilex™ 7 FPGA devices is final, you can safely disregard this warning message. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3. Additional Information Quartus® Prime Pro Edition: Version 25.1 Software and Device Support Release NotesInternal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY
Description Due to a problem in the Quartus® Prime Pro edition software version 26.1 and earlier, you may see this problem when using Synopsys VCS* or VCSMX* simulators to simulate the PIO with MCDMA Bypass Mode example design of F-tile Multichannel DMA IP for PCI Express* in Native Endpoint port mode and Multichannel DMA user mode with either AVMM or AVST interface for MCDMA settings. Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Resolution No workaround is available. This issue will be fixed in a future release of Quartus® Prime Pro edition software.Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?
Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only.