As Cloud Service Providers consider their investment strategies and technology plans for the future, Infrastructure Processing Units (IPUs) offer a path to accelerate and financially optimize cloud services
In a post-pandemic world, one thing has become clear as businesses look to reinvent and rebound: Technology and architecture choices matter more than ever. Leading and winning in this new world has as much to do with the ingenuity of technology choices as it historically has with the business plan. For enterprises, the ability to develop, deploy and scale new services, using next-generation capabilities, at light speed becomes an imperative. For the CSP, this understanding provides an opportunity to take on an increasingly critical role - not just as a technology provider, but as a key strategic business partner. As businesses move at scale to the CSP-provided cloud, there is need to diverge away from server optimized architecture to one better designed to meet the needs of the CSP. This evolution should drive superior levels of optimization to increase both performance and profit. In highly virtualized environments, significant amounts of server resource are expended processing tasks beyond user applications, such as hypervisors, container engines, network and storage functions, security, and vast amounts of network traffic. To address this challenge Intel has introduced a new class of product called the Infrastructure Processing Unit (IPU). An IPU is an advanced networking device with Ethernet connectivity, programmable storage and networking accelerators tightly coupled with dedicated programmable cores that isolates and securely offloads the management of infrastructure functions and other services. An IPU offers full infrastructure offload and provides an extra layer of security by serving as a control point of the host for running infrastructure applications. Leading hyperscale CSPs are driving the following IPU “offloading” use cases: - Accelerated Networking – To offload virtual switch functionality from the host application processor onto the IPU. - Accelerated Storage – To move the storage stack from the host application processor onto the IPU, increasing throughput and reducing complexity and overhead. - Accelerated Security – To offload encryption/ decryption, compression, and other security functions that would otherwise be CPU intensive from the host application processor. - Infrastructure Processing – To offload the hypervisor services management functions from the host application processor down to the IPU. For more information, see IPU-Based Cloud Infrastructure: The Fulcrum for Digital Business For more information about FPGA-based IPUs from Intel and Intel Partners, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others
New video details the secret life of an FPGA
In a new Intel video titled “Architecture All Access: Modern FPGA Architecture,” Intel Fellow Prakash Iyer takes you deep inside of the world of FPGAs. Iyer is a Programmable Solutions Architect who has spent nearly 30 years at Intel as a technology designer and implementer. In this 20-minute video, Iyer takes you on a journey deep inside of an FPGA starting with simple logic gates and then moving up through architecture, design, and applications. Along the way, he answers many questions you might have about FPGAs, even if you’ve worked with FPGAs for years. Some of the questions that Iyer answers in this video include: How does a LUT work? What exactly is an ALM? How does Intel use tiles to build FPGAs? Why harden certain logic functions in an FPGA? What are the differences between a CPU and an FPGA? Where do FPGAs fit in the world of systems design? If you have fundamental questions about FPGAs, chances are that Iyer provides some answers in this video. Click here to check out the video. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Breakthrough FPGA News from Intel
Today, Intel launched the 3 rd Gen Intel® Xeon® Scalable processor, which delivers an average 46% performance improvement on popular data center workloads. 1 The 3 rd Gen Intel Xeon Scalable processors incorporate built-in AI acceleration with Intel® DL Boost technology, Intel® Crypto Acceleration, and advanced security capabilities to protect data and application code with Intel® Software Guard Extensions (SGX). Intel has shipped more than 200,000 units of the 3 rd Gen Intel Xeon Scalable processor for revenue in the first quarter of 2021 with broad industry adoption across all market segments. As part of the numerous portfolio announcements associated with today’s launch, Intel also disclosed some breakthrough FPGA news: Intel® Agilex™ FPGAs now deliver industry-leading power efficiency and performance including: 50% higher video IP performance compared to competing 7nm FPGAs * Approximately 2X better fabric performance per watt compared to competing 7nm FPGAs enabling flexible, energy-efficient designs for the data center and beyond * Intel Agilex FPGAs average 45% faster performance in Data Center, Network, and Edge applications * Up to 49% faster fabric performance compared to prior generation FPGA for high-speed 5G fronthaul gateway applications * The Intel Agilex FPGA family combines the power of Intel’s 10 nm SuperFin process technology, 3D heterogeneous system-in-package (SiP) integration with Intel’s proprietary Embedded Multi-Die Interconnect Bridge (EMIB), and an innovative chiplet-based architecture to deliver customized connectivity and acceleration for a variety of applications. The new architecture allows the FPGA fabric to be stitched together with purpose-built tiles, such as transceivers, processor interfaces, optimized I/O, custom computing, Intel® eASIC™ structured ASICs, and many other functions to create application solutions that are uniquely customized and optimized. Like the the 3 rd Gen Intel Xeon Scalable processor, Intel Agilex FPGAs are currently in production and shipping in volume. For more information about this announcement and about Intel Agilex FPGAs, click here. To watch a brief video about this breakthrough FPGA news, click here. To download the Intel Agilex FPGA product brief, click here. To read the new White Paper titled “Intel® Agilex™ FPGAs Deliver a Game-Changing Combination of Flexibility and Agility for the Data-Centric World,” click on the link. Notices and Disclaimers * Performance varies by use, configuration, and other factors. Learn more at www.Intel.com/PerformanceIndex. 1 See [125] at www.intel.com/3gen-xeon-config. Results may vary. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. Many, many free classes now available for Intel® FPGA training. Pick one (or more)
From now through Q2, 2021, you can avail yourself of many free Intel® FPGA training classes available online. There are currently 424 classes listed, so you’re sure to find something of help. Here are a few representative class titles: The Intel® Quartus® Prime Software: Foundation for Xilinx* Vivado* Design Suite Users Performance Optimization with Intel® Hyperflex™ Architecture Advanced Optimization with Intel® Hyperflex™ Architecture Introduction to High-Level Synthesis with Intel® FPGAs Using Intel® oneAPI Toolkits with FPGAs The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer Using Intel® SoC FPGAs The Intel® Quartus® Prime Software: Foundation High-Level Synthesis Advanced Optimization Techniques Advanced Timing Analysis with Timing Analyzer Timing Closure with Intel® Quartus® Prime Pro Software Click here to check out the current class catalog and schedule. Then, be sure to sign up for the classes that you think will help you the most. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Learn how to use Intel® FPGAs in critical Functional Safety applications: two free on-demand training Webinars
Designs with formal functional safety requirements in markets such as industrial automation, transportation, the smart grid, automotive, military, aerospace, and medical require highly reliable systems that are certified to comply with established safety standards such as IEC 61508 and ISO 13849. Design challenges for such systems include: Adopting quality management standards and implementing a “safe” design methodology Accounting for additional project effort, development time, and technology, which can result in longer time to market and higher cost of ownership The additional steps required to design an application with functional safety certification in mind adds significant project complexity. However, getting immediate access to qualified semiconductor data, intellectual property (IP), development flows, and design tools from Intel can help you significantly shorten your overall project development time. To simplify and speed up the safety certification process, Intel worked closely with TÜV Rheinland to develop an IEC61508 certified Functional Safety Data Package, which includes: Safety manuals for Intel® FPGAs and Intel® Quartus® Prime Design Software Diagnostic and standard intellectual property (IP) such as the Nios® II processor Intel FPGA design flows including a safety separation design flow Development tools, including the Intel Quartus Prime Design Software Two free on-demand training Webinars from Intel can guide you through the process of developing systems that meet functional safety requirements using Intel FPGAs using the Functional Safety Data Package. These Webinars are: Functional Safety for Industrial Applications: Concepts and Regulations This first Webinar provides an overview of functional safety concepts and regulations. The training will allow you to benefit from Intel’s long experience with functionally safe design and will show you how to comply with today’s safety standards. This is a 55-minute Webinar. Functional Safety for Industrial Applications: FPGA advantages, tools and design methodology This second Webinar covers the advantages of using Intel FPGAs for developing systems with functional safety requirements and explains how to maximize these benefits in your next design. This training reviews the use and application of Intel FPGAs and delves into Intel’s TÜV-qualified FPGA design methodology, which greatly reduces development effort, system complexity, and time to market for system designs with functional safety requirements. This is a 65-minute Webinar. Customers who register for and attend these training Webinars will receive an email inviting them to interact with Intel experts via email or to join a live “Ask the Expert” WebEx session. For more information about the functional safety aspects of designing with Intel FPGAs, click here. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel introduces multi-phase, step-down power controller and power stage devices for high-current loads including core rails from 40 A to more than 200 A
Intel has introduced a solution for on-board power rails, including core rails, that incorporates pair of new Intel® Enpirion® power devices. These two new devices make it easy for you to design high-current step-down power converters for power trees with output currents spanning a wide load range from 40 A to more than 200 A, combining high conversion efficiency and PCB space savings with low-risk design. The Intel Enpirion ED8401 digital, multi-phase, step-down controller is designed for non-isolated, high current DC/DC applications. It can control as many as four of the companion Intel Enpirion ET6160 monolithic 70 A power stages with integrated current and temperature monitors. This complete step-down power conversion solution based on these two devices has been designed, tested, and validated on Intel development kits to ensure that they meet the power requirements of a wide variety of FPGAs including Intel® Agilex™, Intel® Stratix® 10, and Intel® Arria® 10 FPGAs; ASICs including Intel® eASIC™ devices; and SoCs. For more information about the Intel Enpirion ED8401 digital, multi-phase, step-down power controller and the Intel Enpirion ET6160 70 A power stage, click here. In addition to powering high-current core rails, Intel Enpirion devices can power your entire power tree with a wide range of solutions. For more information on the whole portfolio, go to www.intel.com/power. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.How Heterogeneous Device Design and Manufacturing Leads to Success
By Patrick Dorsey, Vice President Product Marketing, FPGA and Power Products, Intel The following guest blog is based on remarks by Patrick Dorsey during a panel discussion on “FPGA Hardware Innovations” at the recent The Next FPGA Platform event, held in San Jose, California on January 22, 2020. One of the looming challenges for FPGA hardware design is answering this question: What do you integrate and what do you give up when you integrate? Flexibility matters. FPGA vendors are in the flexibility business. The above question not only matters within the chip, it also matters at the system level. Intel offers many choices to designers of heterogeneous hardware systems. Designers can choose among multiple Intel® Xeon® CPUs. Likewise, they have a choice of several Intel® FPGAs. There’s a lot of value in these choices. Monolithic and heterogeneous integration increase value. Integration in both forms shrinks the overall form factor and improves power consumption. Performance can improve as well. Interfaces can be better optimized. Heterogeneous integration technology enables even more choice. It’s an option at multiple levels within the system. For example, there are a lot of things that we can do with packaging technology, with the interfaces that we have, and with development tools. The options are there. Many things are happening between semiconductor vendors and customers that we can’t talk about publicly. For example, there's a lot of integration that happens with ASICs and with structured ASICs – that’s the Intel® eASIC product. New heterogeneous devices can be manufactured in a customized fashion that could never happen before. Heterogeneous Devices are Here Now Heterogeneous device design and manufacturing is here now. For example, today’s Intel® Agilex™ FPGAs and Intel® Stratix® 10 FPGAs are already heterogeneous FPGAs. We’ve incorporated HBM2 stacked-die DRAM into both types of FPGA. We’ve put the high-speed serial transceivers for these Intel FPGAs on tiles, or chiplets, so that the Ethernet and PCIe protocols are decoupled from the design of the FPGA fabric. The FPGA fabric benefits when moved to new process nodes while interfaces do not. Heterogeneous design allows Intel to innovate in the FPGA fabric and the I/O interfaces separately, and across nodes. We can use multiple nodes to build very complex devices optimally. Another facet is the US government’s involvement with heterogeneous design and manufacturing in these early days. Several DARPA programs are driving research into standalone IP that can sit next to the FPGA. This IP can become chiplets. These chiplets can implement specialized functions in the areas of AI or analog-to-digital converters, for example. The DARPA work is all public. It’s called the CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program. The chiplets concept has advanced very quickly for FPGAs. It’s in volume manufacturing now, as discussed above. However, there are challenges. The first challenge is TDP, thermal design power. The more functions put into the package, the harder it is to get the heat out. So it's primarily a thermal problem but it’s also a business-model problem, which makes it a commercial problem. As soon as you have two or more companies putting their IP into the same device, the business model gets a little more complicated. For example, how you go to market with these mixed-vendor heterogeneous devices? These are some of the challenges for heterogeneous device design and manufacture, but despite these challenges, it's happening now. It Starts with a Great FPGA In terms of the FPGA innovation for heterogeneous device design, it starts with having a great FPGA. All FPGA vendors are trying to build the best FPGA fabric and there are innovations in the ways that the FPGA fabric works. For example, how does the FPGA’s fundamental logic and compute architecture work with memory? One of an FPGA’s key advantages is it’s on-chip memory, which is especially important these days for AI and machine language (ML). For performance reasons, you really want the AI/ML model to fit into the memory in the FPGA package. The next area of innovation is the interconnect, whether it's the heterogeneous interconnect or what happens in the package to solve TDP and power problems. There are things that the US government's doing around the Intel Advanced Interface Bus (AIB), which is an interface that Intel already uses in the Intel Agilex FPGAs and Intel Stratix FPGAs. Intel released the AIB specification into the open-source arena last year and industry organizations like the CHIPS Alliance are pushing the AIB specification as an open industry standard to allow better die-to-die connectivity and to jumpstart the chiplet ecosystem. This may sound funny coming from Intel, but it's not about the semiconductor process alone. Don’t misunderstand that statement. Process technology is extremely important and Intel continues to drive the Moore’s Law process technology cadence. So being on the latest process node is important and I think you'll see FPGAs continuing to lead the charge when it comes to process technology. However, the choices made in the design of a new device really depend on the problems you're trying to solve. You only need to take some functions to the most advanced process node. Some functions, especially I/O functions, can't take advantage of the most advanced process node. Analog functions and memory can’t use the most advanced process nodes. This is where heterogeneous device design and manufacturing shines. Chiplets and heterogeneous devices enable choices. You can choose to advance only the functions that need to go faster while reusing designs that already meet performance and power requirements. Heterogeneous design allows you to make different design tradeoffs – in terms of static power, for example – and power has become critical in the design of every new device. At Intel, we're constantly trying to balance power and performance. Process nodes matter and a mix of process nodes gives you the most design choices by allowing an easy mix of custom IP, standard IP, flexible FPGA IP, and interconnect IP. Heterogeneous design and manufacturing allow Intel to decide how to best mix these technologies to create new semiconductor products. The world's getting more complicated, but Intel has more ways to solve these problems than ever before. Legal Notices and Disclaimers: Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. 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