Silicom Showcases FPGA SmartNIC Acceleration Cards for O-RAN Apps at MWC Barcelona 2022
Silicom specifically designed the Silicom FPGA SmartNIC N6011 as a 5G O-RAN platform using open Intel® technologies. It is custom designed to meet the real-time processing needs of 5G DUs and can be configured for a wide range of network deployments.
Megh Computing demos advanced, scalable Video Analytics Solution portfolio at WWT’s Advanced Technology Center
Megh Computing’s Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization Because Megh’s VAS is scalable, it can handle real-time video streams from a few to more than 150 video cameras. Because it’s flexible, you can use the VAS pipeline elements to construct a wide range of video analytics applications such as: Factory floor monitoring to ensure that unauthorized visitors and employees avoid hazardous or secure areas Industrial monitoring to ensure that production output is up to specifications Smart City highway monitoring to detect vehicle collisions and other public incidents Retail foot-traffic monitoring to aid in kiosk, endcap, and product positioning, and other merchandising activities Museum and gallery exhibit monitoring to ensure that safe distances are maintained between visitors and exhibits Because the number of cameras can be scaled to well more than 100 when using the VAS portfolio, Megh clearly needed a foundational technology portfolio that would support the solution’s demanding video throughput, computing, and scalability requirements. Megh selected a broad, integrated Intel technology portfolio that includes the latest 3 rd Generation Intel® Xeon® Scalable processors, Intel® Stratix® FPGAs, Intel® Core™ processors, and the Intel® Distribution of the OpenVINO™ toolkit. Megh also chose WWT’s Advanced Technology Center (ATC), a collaborative ecosystem for designing, building, educating, demonstrating, and deploying innovative technology products and integrated architectural solutions for WWT customers, partners, and employees to demo the capabilities of the VAS. WWT built and is hosting a Megh VAS environment within its ATC that allows WWT and Megh customers to explore this solution in a variety of use cases, including specific customer environment needs and other requirements. For more information about the Megh VAS portfolio and the WWT ATC, check out the WWT blog here. Notices and Disclaimers Intel is committed to respecting human rights and avoiding complicity in human rights abuses. See Intel’s Global Human Rights Principles. Intel’s products and software are intended only to be used in applications that do not cause or contribute to a violation of an internationally recognized human right. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Intel technologies may require enabled hardware, software, or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.APS Networks launches three OpenBNG Broadband Network Gateways incorporating Intel® Xeon® D processors, Intel® Tofino™ Switch ASICs, and Intel® Stratix® 10 MX FPGAs
Open BNG is an initiative within the Open Optical & Packet Transport (OOPT) Project Group’s Disaggregated Open Routers (DOR) sub-group, which is all part of the global Telecom Infra Project (TIP) that’s working to accelerate the development and deployment of open, disaggregated, and standards-based connectivity technology. TIP announced the initial release of the OpenBNG Technical Requirements document for large scale fiber-to-the-home (FTTH) networks – developed collaboratively by Telefónica, Deutsche Telekom, BT, and Vodafone – last October. The document encompasses: Hardware and software requirements for an open and disaggregated Broadband Network Gateway (BNG) device that operators can deploy in current and future networks for the provision of fixed broadband services (OpenBNG) The role of software-defined networks (SDN) and the desired approach for fixed-mobile convergence The required hardware and proposed non-mutually exclusive software packages needed to support additional services or functionalities Reference regulatory requirements to deploy Open BNG in the networks of the operators participating in the development of this requirements document The OpenBNG specification allows operators a choice of different hardware platforms and types of network operating system (NOS) and control-plane applications, with goals of lowering the total cost of ownership and lowering the cost per broadband subscriber. APS Networks has just launched three BNG switches which aim to comply with TIP OpenBNG requirements. Operators can choose among the SC-1, SC-2, and SC-3 TIP standard configurations for leaf designs that best address their end-user demands and cover both full-functionality deployments and service-only BNG deployments. The APS Networks® announcement includes three BNG products: The Hyperion APS2172Q, supporting 64x1/10/25G BNG user ports & 8x100G spine ports (SC-1) The Jupiter APS6120Q with 16x100G BNG ports & 4x1/10/25G ports (SC-2) The Hyperion APS2140D with 32x1/10/25G BNG user ports & 8x100G spine ports (SC-3 leaf) The APS2172Q and APS6120Q each support as many as 32,000 broadband subscribers and the APS2140D supports as many as 20,000 broadband subscribers. The announced BNG switches incorporate Intel® Xeon® D processors, P4-programmable Intel® Tofino™ Ethernet switch ASICs, and Intel® Stratix® 10 MX FPGAs with High-Bandwidth Memory (HBM). All BNG switch models can be equipped with a Precision Time Protocol (PTP) IEEE 1588v2 compliant add-on module, which enables the switches to operate as PTP boundary clocks with end-to-end accuracies of better than 10nsec. Andy Heal, Chief Technology Officer for APS Networks, said “The APS Networks range of OpenBNG switches accelerate the possibilities for access edge solutions. Combining these low latency products of Intel Tofino P4-programmable switch ASICs and Intel Stratix 10 MX FPGAs, with world-class PTP capabilities and Intel Xeon D processors, APS Networks have designed and developed a unique range of network switches for the wireline broadband market.” For more information about these APS Networks OpenBNG switches, please contact APS Networks directly. Click here. For more information about Intel Xeon D processors, click here. For more information about the Intel Tofino Ethernet Switch ASIC, click here. For more information about Intel Stratix 10 FPGAs including the Intel Stratix 10 MX FPGAs, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, Xeon, Tofino, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.IEEE FPGA Workshops and Tutorials featuring Intel speakers, May 9-13
The virtual 29th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) takes place online from May 9-12. Intel speakers will be presenting several workshops and tutorials at this conference including: Intel FPGA Cloud Services and Remote Learning – Workshop – May 9 AI Optimized Intel® Stratix® 10 NX FPGA – Tutorial – May 12 Using Intel® oneAPI Toolkits with FPGAs – Workshop – May 12 For more information about these IEEE FCCM workshops and tutorials including registration details, click here. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Can FPGAs outperform GPUs for some AI workloads? Answer: Yes
For many AI workloads, it can be challenging to achieve the full compute capacity reported by GPU vendors. Even for highly parallel computation such as general matrix multiplication (GEMM), GPUs can only achieve high utilization at certain large matrix sizes. FPGAs offer a different approach to AI-optimized hardware. Unlike GPUs, FPGAs offer unique fine-grained spatial reconfigurability where the output of each function can be routed directly to the input of the function that needs it. This approach allows greater flexibility to accommodate specific AI algorithms and application characteristics that enable improved utilization of available FPGA compute capabilities and, therefore, improved performance. Specialized soft processors, also called overlays, allow FPGA programming in a fashion similar to processors, where the FPGA programming is done purely via software toolchains. This programming approach abstracts away FPGA-specific hardware complexity. A new White Paper titled “Real Performance of FPGAs Tops GPUs in the Race to Accelerate AI” presents the first performance evaluation of the new Intel® Stratix® 10 NX FPGA in comparison to the Nvidia T4 and V100 GPUs. This performance evaluation was conducted over a suite of real-time inference workloads, based on results published in a paper presented at the 2020 IEEE International Conference on Field Programmable Technology. The workloads for the FPGA were deployed using an implementation of a soft AI processor overlay called the Neural Processing Unit (NPU) with a tool chain that enables software-centric FPGA programming without invoking FPGA-specific hardware EDA tools. Results show that the Intel Stratix 10 NX FPGA achieves far better utilization and performance than the tested GPUs for these AI workloads. Want the details? Click here to download the White Paper. Notices and Disclaimers Intel technologies may require enabled hardware, software, or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Free Webinar: Using Intel® oneAPI™ to Achieve High-Performance Compute Acceleration with FPGAs
Interested in learning how to use the Intel® oneAPI™ open, unified programming model to accelerate data-centric workloads using FPGAs? Then sign up for the free Webinar titled “Using Intel oneAPI to Achieve High-Performance Compute Acceleration with FPGAs.” It’s being presented on March 23 and March 25 by Intel and Bittware. The Webinar will zero in a real-world, 2D FFT workload accelerated by BittWare's 520N-MX PCIe acceleration card based on the Intel® Stratix® 10 MX FPGA. This Intel FPGA incorporates high-performance HBM2 memory, which delivers additional acceleration speed. The Webinar will discuss: How the Intel oneAPI unified programming model enables easier, software-like FPGA workload acceleration development A look at BittWare's accelerated 2D FFT code A discussion of various development tools including the Intel® Vtune™ Profiler, which optimizes application performance, system performance, and system configuration for HPC, cloud, IoT, media, storage, and more A preview of next-generation acceleration cards like BittWare's IA-840F, which is based on the Intel® Agilex™ FPGA. A live Q&A with the Webinar’s four panelists from Intel and Bittware Intrigued? Register for either Webinar by clicking the links below: Tuesday March 23: 8:30am UK/4:30am Eastern (time targets EU/Asia) Thursday March 25: 6:30pm UK/2:30pm Eastern (time targets Americas) Note: If you can't make the live event, register anyway and you will get access to the on-demand Webinar recording. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Biz Tech thought leader Dez Blanchfield’s recent podcast discusses infrastructure and application acceleration using FPGAs, SmartNICs, and Intel® eASIC™ structured ASICs with Intel’s Jim Dworkin
Business and digital transformation strategy thought leader Dez Blanchfield regularly posts podcasts in a series titled “Conversations with Dez” about topics of interest to the technology industry. He recently interviewed Jim Dworkin, Senior Director of the Cloud Business Unit in the Programmable Solutions Group at Intel and the two have a wide-ranging discussion that touches on data center architecture and making FPGAs easier to use to accelerate various workloads at scale within the data center. The two also discuss the roles of FPGA-based SmartNICs, which can “hard wire” data flows within the data center to build strategic pathways to reduce data movement, accelerate processing rates, speed time to market, and lower total costs of ownership. In addition, their discussion covers the broader use of Intel® FPGAs and Intel® eASIC™ structured ASICs, the new AI-optimized Intel® Stratix® 10 NX FPGA, and the use of Intel® Open FPGA Stack (Intel® OFS) and Intel® oneAPI toolkits to ease the adoption of all forms of Intel® XPU acceleration including FPGAs. The hour-long interview is now available on SoundCloud. Click here to listen. For more information about the AI-optimized Intel Stratix 10 NX FPGA, see “Intel has just announced its first AI-optimized FPGA – the Intel® Stratix® 10 NX FPGA – to address the rapid increase in AI model complexity” and “More details on the Intel® Stratix® 10 NX FPGA, the first AI-optimized Intel® FPGA, now available in a new White Paper.” For more information about Intel OFS, see “Intel® Open FPGA Stack Eases Development of Custom Acceleration Platform Solutions.” For more information about Intel oneAPI, see “Intel’s One API will allow you to write code once, then target many processing resources: CPUs, GPUs, FPGAs, AI engines.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel® Quartus® Prime Pro Edition Version 20.4 Software Now Ready for Download
Intel® Quartus® Prime Pro Edition Version 20.4 Software is now available for download. In addition to functional and security updates, the new development software for Intel® FPGAs incorporates many new features including: Partial reconfiguration and encrypted partial reconfiguration bitstream support Intel Stratix® 10 devices Enhanced handling of Intel FPGA designs with large inferred RAM requirements Platform Designer enhancements include: ► Added support for system HDL parameters. Now you can pass parameter values from parent systems to subsystems and from system to instantiated IP blocks by adding HDL parameters to systems and assigning values to instance HDL parameters that are exposed. ► Added new interconnect parameter: Enable all pipeline stages. ► Added “Add All Pipelines” and “Remove All Pipelines” buttons to MemoryMapped Interconnect tab. To go directly to the Intel Quartus Prime Pro Edition download page, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.FPGA-based reference design from Algo-Logic and Intel cuts high-speed financial trading latency by 3.8X
Algo-Logic and Intel have developed a high-speed reference framework design that offloads the network stack required for high-speed financial trading to logic instantiated in an Intel® Stratix® 10 FPGA on the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) D5005 platform. The reference design includes: A fast PCIe interface (the Algo-Logic Fast Data Mover) A C/C++ to FPGA business logic implementation area that serves as a target for logic developed using high level synthesis (HLS) A TCP/IP offload engine An ultra-low-latency (ULL) 10GbE media access control (MAC) According to the conclusion in a new White Paper titled “Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005,” the reference design achieves 3.8X lower latency compared to a design with just an Ethernet offload engine. 1 These innovations significantly accelerate low-latency trading system development while offering the flexibility to add proprietary trading algorithms to the FPGA. Click on the link above for more technical details. Notices & Disclaimers 1. Testing by Algo-Logic on October 26, 2020. Server configuration: HPE DL380 G10, CPU = Intel® Xeon® Gold processor 6154 @ 3.00 GHz; DRAM = 128 GB total, and RHEL* 7.6. Production Intel FPGA PAC D5005. For more information, a benchmark report is available under NDA. Contact your sales rep for more information. Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
