IEEE 802.1 TSN IP and software from TTTech Industrial now available packaged with selected Cyclone® V SoC FPGAs
Time Sensitive Networking (TSN) is the IEEE 802.1 standard for deterministic packet transmission and handling over Ethernet networks. It is a set of evolving IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections; provides precise time synchronization of network nodes using synchronized, distributed local clocks; and serves as the network foundation for smart factories, Industry 4.0, and Intelligent Internet of Things (IIoT) applications. Intel is now offering special TSN versions of three Cyclone® V SoC FPGAs that include TTTech Industrial’s TSN Edge IP Solution with both an IP core and the embedded software required to build a TSN switch. There are no up-front license fees, no per-unit royalty reporting, and no protracted negotiations for the TTTech Industrial IP or software when the Cyclone V SoC FPGAs are purchased through Intel or its authorized distributors. Three Cyclone V SoC FPGAs are available packaged with the TTTech Industrial TSN Edge IP solution: Cyclone V SE SoC FPGA, U484 package (19mm), OPN: 5CSEBA6U19I7NTS Cyclone V SE SoC FPGA, U672 package (23mm), OPN: 5CSEBA6U23I7NTS Cyclone V SX SoC FPGA, U672 package (23mm), OPN: 5CSXFC6C6U23I7NTS For more details including ordering instructions, click here. For more information on implementing and using TSN in Intel FPGAs, see “Time Sensitive Networking: From Theory to Implementation in Industrial Automation.” Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
Accelerate NFVi Workloads For 5G Deployments Webinar: Watch On-Demand Now
The recently-held “Accelerate NFVi Workloads For 5G Deployments” webinar highlights the collaboration between Juniper Networks, HCL Technologies, and Intel® to solve network performance challenges and allow Contrail users to experience increased overall server performance and utilization for vRouter-based infrastructures in telecommunications environments.FPGA-Based Cloaking and Security Tech Helps Protect Equipment on IT and OT Networks from the Bad Guys
You can’t attack what you can’t see, and cloaking technology for devices on Ethernet LANs is merely one of many protection layers implemented in Q-Net Security’s Q-Box to protect networked devices and transaction between these devices from cyberattacks. Other security technologies built into the Q-Box include encryption, authentication, and the use of different, randomly generated security keys created just in time for each transaction – called JITKeys – with no external key management. Adding security to a networked device is as simple as placing a small Q-Box between a protected device and its LAN using an extra RJ45 cable. Each Q-Box can protect as many as 2000 network endpoints, allowing operators to create protected LAN segments throughout a larger network. Connect the Q-Box to a WAN router and the protected LAN segments can be located anywhere in the world. You can use the Q-Box to protect a wide range of networked devices including: Servers and PCs on IT networks Financial equipment ranging from ATMs in banks to slot machines in casinos Equipment connected to Operational Technology (OT) networks in buildings, factories, refineries, and utilities including PLCs and other industrial controllers, lighting systems, security systems and cameras, and even robotic equipment The Q-Box can secure any device on an Ethernet LAN. The Q-Box works with all networked devices including legacy systems. Face it. Cyberspace is getting more dangerous every day. Need proof? Here are just a handful of recent cyberattacks: December, 2020: Hackers inserted malicious code into SolarWinds’ Orion software, exposing sensitive and critical data at top government agencies including parts of the Pentagon, the Department of Homeland Security, the State Department, the Department of Energy, the National Nuclear Security Administration, and the Treasury; corporations including systems Microsoft, Cisco, Intel, and Deloitte; and other organizations including the California Department of State Hospitals, and Kent State University. 1 February, 2021: A Hacker attempted to poison the drinking water supply for Oldsmar, Florida by dangerously increasing sodium hydroxide levels in the water. 2 March, 2021: Hackers compromised more than 150,000 security cameras located in gyms, jails, schools, hospitals, and factories. 3 May, 2021: The DarkSide Russian hacking group forced Colonial Pipeline to cut the connection between its IT and OT networks, shutting down the company’s 5500-mile pipeline for several days and causing massive gasoline shortages on the US east coast. 4 Q-Net implemented the secure technology inside of the Q-Box using the programmable hardware in an Intel® Cyclone® FPGA. The Q-Box provides access protection without requiring changes or additions to an endpoint’s legacy code and with no modifications to existing equipment. In addition, the FPGA-based hardware in the Q-Box does not require and does not permit software updates or patches from the network. The network security protection it supplies is immutable. Because it’s implemented in hardware on an FPGA, the Q-Box introduces only a few microseconds of network latency. For more information about Q-Net Security’s Q-Box, click here. Notices and Disclaimers “SolarWinds Hack Victims: From Tech Companies to a Hospital and University,” The Wall Street Journal, https://www.wsj.com/articles/solarwinds-hack-victims-from-tech-companies-to-a-hospital-and-university-11608548402 “A Hacker Tried to Poison a Florida City's Water Supply, Officials Say,” Wired, https://www.wired.com/story/oldsmar-florida-water-utility-hack/ “Hackers just pulled off one of the most mind-boggling hacks of 2021 so far,” BGR Media, https://bgr.com/tech/security-cameras-hacked-verkada-customers-exposed/ “Intel® Agilex® FPGAs target IPUs, SmartNICs, and 5G Networks,” https://www.intel.com/content/dam/www/central-libraries/us/en/documents/agilex-fpgas-target-ipus-smartnics-5g-networks-white-paper.pdf Intel technologies may require enabled hardware, software or service activation. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.APS Networks launches three OpenBNG Broadband Network Gateways incorporating Intel® Xeon® D processors, Intel® Tofino™ Switch ASICs, and Intel® Stratix® 10 MX FPGAs
Open BNG is an initiative within the Open Optical & Packet Transport (OOPT) Project Group’s Disaggregated Open Routers (DOR) sub-group, which is all part of the global Telecom Infra Project (TIP) that’s working to accelerate the development and deployment of open, disaggregated, and standards-based connectivity technology. TIP announced the initial release of the OpenBNG Technical Requirements document for large scale fiber-to-the-home (FTTH) networks – developed collaboratively by Telefónica, Deutsche Telekom, BT, and Vodafone – last October. The document encompasses: Hardware and software requirements for an open and disaggregated Broadband Network Gateway (BNG) device that operators can deploy in current and future networks for the provision of fixed broadband services (OpenBNG) The role of software-defined networks (SDN) and the desired approach for fixed-mobile convergence The required hardware and proposed non-mutually exclusive software packages needed to support additional services or functionalities Reference regulatory requirements to deploy Open BNG in the networks of the operators participating in the development of this requirements document The OpenBNG specification allows operators a choice of different hardware platforms and types of network operating system (NOS) and control-plane applications, with goals of lowering the total cost of ownership and lowering the cost per broadband subscriber. APS Networks has just launched three BNG switches which aim to comply with TIP OpenBNG requirements. Operators can choose among the SC-1, SC-2, and SC-3 TIP standard configurations for leaf designs that best address their end-user demands and cover both full-functionality deployments and service-only BNG deployments. The APS Networks® announcement includes three BNG products: The Hyperion APS2172Q, supporting 64x1/10/25G BNG user ports & 8x100G spine ports (SC-1) The Jupiter APS6120Q with 16x100G BNG ports & 4x1/10/25G ports (SC-2) The Hyperion APS2140D with 32x1/10/25G BNG user ports & 8x100G spine ports (SC-3 leaf) The APS2172Q and APS6120Q each support as many as 32,000 broadband subscribers and the APS2140D supports as many as 20,000 broadband subscribers. The announced BNG switches incorporate Intel® Xeon® D processors, P4-programmable Intel® Tofino™ Ethernet switch ASICs, and Intel® Stratix® 10 MX FPGAs with High-Bandwidth Memory (HBM). All BNG switch models can be equipped with a Precision Time Protocol (PTP) IEEE 1588v2 compliant add-on module, which enables the switches to operate as PTP boundary clocks with end-to-end accuracies of better than 10nsec. Andy Heal, Chief Technology Officer for APS Networks, said “The APS Networks range of OpenBNG switches accelerate the possibilities for access edge solutions. Combining these low latency products of Intel Tofino P4-programmable switch ASICs and Intel Stratix 10 MX FPGAs, with world-class PTP capabilities and Intel Xeon D processors, APS Networks have designed and developed a unique range of network switches for the wireline broadband market.” For more information about these APS Networks OpenBNG switches, please contact APS Networks directly. Click here. For more information about Intel Xeon D processors, click here. For more information about the Intel Tofino Ethernet Switch ASIC, click here. For more information about Intel Stratix 10 FPGAs including the Intel Stratix 10 MX FPGAs, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, Xeon, Tofino, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.The Next Platform discusses the latest Intel Networking Innovations including new Intel® SmartNICs based on Intel® FPGAs
Last month, Intel introduced several FPGA-based networking innovations, including the Intel® FPGA SmartNIC C5000X platform architecture – designed to meet the needs of Cloud Service Providers. Also announced: the Inventec FPGA SmartNIC C5020X, based on the Intel FPGA SmartNIC C5000X platform, and the Silicom FPGA SmartNIC N5010, a hardware-programmable 4x100G FPGA SmartNIC that combines an Intel® Stratix® 10 DX FPGA with an Intel® Ethernet 800 series adapter. (See “Intel and partners announce high-performance SmartNICs that deliver programmable network acceleration for cloud data centers and communications infrastructure.”) The Next Platform – an online publication dedicated to covering high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds – discusses these and other network-related introductions from Intel in an article titled “Intel Networking: Not Just A Bag Of Parts,” written by the publication’s co-editor Timothy Prickett Morgan. The article features quotes from an interview with Hong Hou, Corporate Vice President and General Manager of the Connectivity Group at Intel, and it contains a large amount of analysis of the announced Intel networking innovations and offerings. Early in the article, Prickett Morgan had this to say: “Here is the reality: Companies will splurge on compute, by which we generally mean CPUs but increasingly GPUs and occasionally FPGAs, rather than memory or networking because they understand it better. Here is another fact that cannot be bargained with: The amount of data that is being shuttled around by networks in the datacenter is growing at 25 percent per year. But budgets cannot grow at that rate… “…it absolutely is desirable to have Intel be in the networking business and bring what it knows about the datacenter to bear.” Prickett Morgan then quotes from his interview with Hou: “For Intel, we want to provide intelligence and programmability in a flexible network that can handle the complexity of the emerging workloads. Our vision is to optimize all of these technology assets to provide enabling solutions for our customers – we are not just a supplier of a bag of parts.” Although the scope of these Intel offerings is quite wide and therefore hard to sum up in a few words, Prickett Morgan makes the effort. With respect to the FPGA-based introductions made last month, he writes: “What is interesting here is that the new Intel SmartNICs are not actually made by Intel, but by Inventec and Silicom, the former being an increasingly important ODM for hyperscalers and cloud builders and the latter being a network interface supplier for the past two decades. These devices sit on a spectrum along with the pure FPGA acceleration card, called the Programmable Acceleration Card, which we talked about when it first debuted with the [Intel® Arria® 10 FPGA] in October 2017 and when it was updated in September 2018 with the [Intel] Stratix 10 FPGA.” To read Timothy Prickett Morgan’s full article in The Next Platform, click here. For an associated editorial about these networking topics written by Hong Hou, see “Smart, Programmable Interconnects Unleash Compute Performance” in the Intel Newsroom. For more information about the October 15 Intel Networking event, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel and partners announce high-performance SmartNICs that deliver programmable network acceleration for cloud data centers and communications infrastructure
Intel has been a leader in Ethernet networking since the very beginnings of the IEEE 802 standard. The first Ethernet specification, Version 1.0, was published on September 30, 1980 – forty years ago. It was submitted as a candidate for the active IEEE project 802 local area network standardization effort. The original Ethernet specification document was called the “Blue Book” because of the light blue cover on the printed specification. Three company names appeared on that cover. One of those three names was Intel. Last week, just slightly more than forty years after the publication of that first Ethernet specification, Intel and its partners announced new, high-performance SmartNIC products that deliver programmable network acceleration for cloud data centers and communications infrastructure. The first such network acceleration product is the Inventec FPGA SmartNIC C5020X, which is based on the new Intel FPGA SmartNIC C5000X platform architecture designed to meet the needs of Cloud Service Providers. This new architecture boosts data center performance levels by off-loading switching, storage, and security functionality onto a single PCIe platform that combines both Intel FPGAs and Intel Xeon® processors. Customers can define and port custom networking functions to the Intel Stratix 10 FPGA. The familiarity of the Intel® Xeon-D processor integrated into the platform eases the porting effort. Inventec is one of the first ecosystem partners to leverage the Intel FPGA SmartNIC C5000X platform architecture. The second new SmartNIC is the Silicom FPGA SmartNIC N5010, a hardware-programmable 4x100G FPGA SmartNIC that combines an Intel Stratix 10 DX FPGA with an Intel® Ethernet 800 series adapter. The FPGA-based SmartNIC features enhanced packet buffering and traffic flow monitoring while extending connectivity to multiple 100G Ethernet ports. The Silicom FPGA SmartNIC N5010 delivers the performance and hardware programmability that Communications Service Providers need to accelerate 25G and 100G networks and Intel is partnering with Silicom to deliver this SmartNIC. The Intel FPGA SmartNIC C5000X platform and the new Silicom FPGA SmartNIC N5010 allow data center architects and network engineering teams at Telecom Equipment Manufacturers (TEMs), Virtual Network Function (VNF) vendors, system integrators, and telcos to supercharge their networks and to free up server CPU cycles for revenue-generating workloads. New SmartNIC products based on Intel® Stratix™ 10 FPGAs, Xeon-D processors, Intel Ethernet 800 series network adapters, and new platform architectures such as the Intel® FPGA SmartNIC C5000X platform help accelerate cloud data centers and communications infrastructure. Here are some quotes from Inventec, Silicom, other network ecosystem partners, and customers about these new SmartNIC products: “FPGAs have been the core of Azure’s SmartNIC infrastructure for multiple generations, providing us a high performance, flexible, and differentiated solution,” says Derek Chiou, a Partner Architect at Microsoft. “We are pleased to see Intel continue to lead the industry by launching the ground-breaking Intel FPGA SmartNIC Platform C5000X that will enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency, while providing flexibility to suit their needs.” continuing to lead the industry by launching the ground-breaking Smart NIC platform in Big Spring Canyon that can help ecosystem partners to enable cloud service providers to integrate FPGA technology in their data centers to increase their efficiency while providing flexibility to suit their own needs.” “Inventec is proud to have partnered with Intel to create a unique SmartNIC based upon the Intel® FPGA SmartNIC C5000X platform architecture,” says George Lin, General Manager of Business Unit VI, Inventec Enterprise Business Group (Inventec EBG). “We immediately realized that this platform would stand out as the SmartNIC for the future, offering customers the ability to customize while still delivering the outstanding performance, programmability, and portfolio of technology that only Intel can provide” “As a leading provider of connectivity solutions, it’s clear that SmartNICs can dramatically improve the performance and efficiency of 4G/5G edge deployments for Telco providers,” said Boris Beletsky, AVP, Emerging Technologies. "The Silicom FPGA SmartNIC N5010 is the first hardware programmable 200G FPGA accelerated SmartNIC that enables next generation IA-based servers to meet the performance and scaling needs of the 5G core network (UPF), access gateways (BNG, AGF), and security functions (Firewall, IPsec)." “Kaloom’s Programmable Networking Fabrics enable Telcos, Data Center Operators and CSPs to accelerate performance and monetization of millions of subscribers at the “Edge”, combining state of the art P4-enabled Intel Tofino switches, Stratix 10 FPGAs and Xeon processors in a fully virtualized manner (“slicing”)”, said Philippe Michelet, VP of Product Management. “By specifically leveraging Intel Stratix 10 FPGAs with integrated HBM2 memory running on the Silicom FPGA SmartNIC N5010, Kaloom can support several millions of subscribers as well as the statistics required by operators to correctly account for the data being processed by this new category of “Edge” data centers.” Click here for a fact sheet with more information about these announcements. Click here for more information about SmartNIC products from Intel. For more information about the Intel FPGA SmartNIC C5000X Platform, see the Solution Brief titled “Accelerate Your Data Center with Intel® FPGAs.” For more information about the Silicom FPGA SmartNIC PN5010, see the Solution Brief titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Free Webinar: Unlock the Benefits of Time Sensitive Networking (TSN) with FPGAs in Industrial Applications
Time-Sensitive Networking (TSN) – the evolving set of IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections – provides precise time synchronization of network nodes using synchronized, distributed local clocks. It’s increasingly being used for smart factories, Industry 4.0, and Intelligent Internet of Things (IIoT) applications. If you want to build TSN into your equipment designs, Intel® FPGAs are a good choice. Looking for an easy way to wade into the topic? Intel and Arrow have you covered with a free Webinar titled: “Unlock the Benefits of Time Sensitive Networking (TSN) with FPGAs in Industrial Applications,” presented by Dr. Joshua Levine from Intel and Dr. Patrick Loschmidt from TTTech. The Webinar covers: What TSN is and how it works The Open Platform Communications (OPC) Unified Architecture (UA) How TSN can be used for Industrial Automation and other applications The Intel TSN offering Detailed look at TSN solutions based on Intel FPGAs The Webinar kicks off on October 19, but even if you can’t make that date and time, register anyway and you’ll get access to a recording of the presentation so that you can watch at your convenience. Register here. For more information about TSN and Intel FPGAs, see “IEEE 802.1 TSN IP and software from TTTech Industrial now available packaged with selected Cyclone® V SoC FPGAs.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Free Webinar: Offload Hyperscale DDoS Attacks to SmartNICs and see a 300X performance improvement. July 30
Distributed Denial of Service (DDoS) attacks are increasing in size, complexity, and severity. Service providers demand virtual security solutions that offer flexible and robust defenses against these increasingly frequent attacks. The F5 Networks BIG-IP VE for SmartNICs solution instantiated on an Intel® FPGA Programmable Acceleration Card N3000 can handle large DDoS attacks – as much as 300X larger – than software-only implementations while reducing TCO by approximately 47%. Now you can learn more about this powerful cloud and enterprise security solution in a free Webinar being held on July 30. The Webinar is jointly sponsored by F5 and Intel. Click here for more details and registration information. For additional details about this solution, see “F5 Networks BIG-IP VE for SmartNICs uses Intel® FPGA Programmable Acceleration Card N3000 to efficiently block incoming DDoS attacks in cloud environments while lowering TCO.” Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. F5 Networks BIG-IP VE for SmartNICs uses Intel® FPGA Programmable Acceleration Card N3000 to efficiently block incoming DDoS attacks in cloud environments while lowering TCO
Tom Atkins, a Product Marketing Manager at F5 Networks, has just published a blog that describes the company’s fully integrated BIG-IP Virtual Edition (VE) solution, which efficiently blocks incoming Distributed Denial of Service (DDoS) attacks in cloud environments using hardware acceleration to realize significant performance and total cost of ownership (TCO) gains. The solution consists of the F5 Networks BIG-IP AFM (Advanced Firewall Manager) Virtual Edition integrated with the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 SmartNIC. In his blog, Atkins says that the combination of the F5 Networks BIG-IP AFM and the Intel FPGA PAC N3000 SmartNIC frees up CPU cycles for other functions and improves overall DDoS mitigation capacity. The result: The F5 Networks BIG-IP VE solution can handle DDoS attacks as much as 300X larger than software-only implementations while reducing TCO by approximately 47% by migrating CPU-intensive DDoS mitigation tasks including network threat intelligence, machine learning, packet-based analysis and white listing to the SmartNIC, which frees up high-value CPU cores to run revenue-generating cloud applications instead. For more information, read Atkins’ blog titled “Mitigate DDoS Attacks up to 300x Greater in Magnitude in Cloud Environments: Introducing BIG-IP VE for SmartNICs,” and then watch the associated 10-minute video from F5 Networks titled “Boosting BIG-IP VE Performance with Hardware Acceleration Technologies.” The video features F5 Networks Senior Strategic Architect Jason Rahm, who delves even further into the technical details of this topic. (Note: In the video, Rahm states that the F5 Networks BIG-IP AFM VE solution with the Intel® FPGA PAC N3000 SmartNIC delivers a 70X performance boost over a software-only implementation, but a footnote in the video’s description states that more recent testing has yielded performance improvements as large as 300X.) Also, please see the associated Solution Brief titled “High Capacity DDoS Protection in Cloud Environments with F5 BIG-IP VE for SmartNICs and Intel FPGA PAC N3000.” For more information about the Intel FPGA PAC N3000, click here. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. Hot Chips 2020 Conference (August 16-18) announces program including several Intel presentations covering server and mobile processors, FPGAs, quantum computing, and a Jim Keller keynote
Do you need to keep up with the latest developments in processor, chip architecture, semiconductor, and advanced computing technology? The annual Hot Chips conference has been the place to surf technology’s leading edge for the last 30 years – and this year is no exception. At this year’s Hot Chips conference, now scheduled for August 16 through 18 as a live, virtual event due to the worldwide COVID-19 situation, you can hear about breakthrough, cutting-edge technologies used to develop processors, semiconductor process technology, and even quantum computing from the comfort of your favorite easy chair. Sunday, August 16 is a tutorial day followed by two days of conference presentations. The Hot Chips 2020 Committee has just posted this year’s program, which includes several presentations from Intel: The first conference day, on Monday, August 17, includes a keynote presentation by Jim Keller – senior vice president of Intel’s Technology, Systems Architecture and Client Group and general manager of Intel’s Silicon Engineering Group. Keller has a long and storied history closely tied to the development of microprocessor architectures and he has been an outspoken advocate regarding the continuation of Moore’s Law into the future. His presentations never fail to both inform and entertain. Additional Intel presentations during the conference itself include: “Next Generation Intel Xeon(R) Scalable Server Processor: Icelake-SP” by Irma Esmer Papazian “Inside Tiger Lake: Intel’s Next Generation Mobile Client CPU” by Jumnit Hong “The Xe GPU Architecture” by David Blythe “Agilex Generation of Intel FPGAs” by Ilya Ganusov “Tofino2 – A 12.9Tbps Programmable Ethernet Switch” by Anurag Agrawal and Changhoon Kim (Intel/Barefoot Networks) In addition, during the August 16 pre-conference tutorial day, James S. Clarke from Intel will give a presentation titled “Towards a Large-scale Quantum Computer Using Silicon Spin Qubits” during a Sunday tutorial session on quantum computing. These Intel presentations represent the broad topic spectrum that’s always on offer during a Hot Chips conference. To check out the Hot Chips 2020 program, click here. To register, click here. Early registration pricing for the live, virtual conference is available through the end of May. (All sessions will be recorded for later viewing as well.) Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Note: If circumstances change and permit Hot Chips to be held as a physical conference, the Hot Chips organization will alert registrants and will offer them option of upgrading. Registration fees for a physical conference have not been set. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.