Learn to use Data Parallel C++ to accelerate MapReduce processing at this ISC oneAPI Dev Summit session on June 23
Many workloads have inherent data parallelism which can be leveraged to achieve optimal performance. However, it is challenging to design data parallel programs and map them to different hardware targets. Data Parallel C++ (DPC++) is an open alternative for cross-architecture development, aiming to address this challenge. A session titled “Word-Count with MapReduce on FPGA, A DPC++ Example” at the upcoming ISC oneAPI Dev Summit, a two-day live virtual conference, discusses the MapReduce distributed programming model for large datasets and how to accelerate MapReduce processing using FPGAs and DPC++. The tutorial will be presented by Dr. Yan Luo, a Professor in the Department of Electrical and Computer Engineering at the University of Massachusetts Lowell. Dr. Luo’s research spans computer architecture, machine learning and data analytics. He teaches undergrad and graduate courses on topics such as embedded systems and heterogeneous computing. To register for the oneAPI Dev Summit (June 22-23) and Dr. Luo’s DPC++ tutorial (June 23), click here. For more information about DPC++, see: Intel’s ‘One API’ Project Delivers Unified Programming Model Across Diverse Architectures Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy! Free Webinar: Accelerate FPGA Programming using Data Parallel C++ (DPC++) and the Intel® oneAPI Base Toolkit with the Intel® FPGA Add-on Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Free Webinar: Accelerate FPGA Programming using Data Parallel C++ (DPC++) and the Intel® oneAPI Base Toolkit with the Intel® FPGA Add-on
Are you curious about using Intel® oneAPI and Data Parallel C++ (DPC++) to develop FPGA accelerators? Sign up for this free Webinar that will show you how to use two free tools – the Intel® oneAPI Base Toolkit (Base Kit) and the Intel® FPGA Add-on for the oneAPI Base Toolkit – to speed programming of Intel® FPGAs. Webinar topics include: How the Intel oneAPI Base Kit enables functional verification through quick emulation and rapid performance tuning How to develop a Hough Transform algorithm, a feature extraction method used in computer vision applications, using DPC++ The steps necessary to generate FPGA binaries Using the Intel FPGA Add-on tool to run a pre-compiled bitstream to observe the algorithm's performance on real FPGA accelerator hardware Register for the Webinar here. For more information about Intel oneAPI and DPC++, see “Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!
Data Parallel C++ (DPC++) is an open-source compiler project based on the Khronos SYCL compiler with a few extensions. It is also the foundation compiler technology for oneAPI, a cross-industry, open, standards-based unified programming model that delivers a common developer experience across accelerator architectures. SYCL is an industry-driven Khronos programming language standard that adds data parallelism to the C++ language with support for heterogeneous computing architectures. The DPC++ language also offers broad, heterogeneous support for CPUs, GPUs, and FPGAs – which is why it’s the compiler at the core of the oneAPI specification. Springer has just published new book titled “Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL” under its Apress open-access imprint. The book’s authors include James Reinders, a consultant with more than three decades of parallel computing experience, and five additional authors from Intel. A printed version of the book is now on sale online and a free PDF version is available on the SpringerLink Web site under the Creative Commons Attribution 4.0 International License. This new 548-page book covers programming for data parallelism using C++ in depth. All examples in the book starting with the “Hello Data-Parallel Programming World” example in Chapter 1 compile and work with DPC++ compilers and are available from a GitHub repository. The book is for all software developers, whether they’re new to parallel programming or old hands at it. As the authors write in the book’s preface: “If you are new to parallel programming, that is okay. If you have never heard of SYCL or the DPC++ compiler, that is also okay.” For readers of this Programmable Logic blog, Chapter 17 titled “Programming for FPGAs” will be especially interesting. As the authors explain in Chapter 17’s second paragraph: “Field Programmable Gate Arrays (FPGAs) are unfamiliar to the majority of software developers, in part because most desktop computers don’t include an FPGA alongside the typical CPU and GPU. But FPGAs are worth knowing about because they offer advantages in many applications. The same questions need to be asked as we would of other accelerators, such as “When should I use an FPGA?”, “What parts of my applications should be offloaded to FPGA?”, and “How do I write code that performs well on an FPGA? “This chapter gives us the knowledge to start answering those questions…” For more information about “Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL,” and to download a free PDF copy of the book, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.