Why is there a port width mismatch on d2h_usr_desc_cdt_avail_cnt in the generated top-level wrapper of the AXI Multichannel DMA IP for PCI Express*?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, the generated top-level wrapper (*_inst.v) for the AXI Multichannel DMA IP for PCI Express* exports an incorrect port width for d2h_usr_desc_cdt_avail_cnt when the D2H Descriptor Engine Credit Interface is enabled.

For example, when Maximum D2H Descriptor Fetch (d2h_max_num_desc_fetch_hwtcl) is set to 64, the generated wrapper defines d2h_usr_desc_cdt_avail_cnt as a 6-bit output ([5:0]) instead of a 7-bit output ([6:0]).

Resolution

To work around this problem in the Quartus Prime Pro Edition software version 26.1.1, manually update the d2h_usr_desc_cdt_avail_cnt port width in the generated top-level wrapper (*_inst.v).

The expected port width of d2h_usr_desc_cdt_avail_cnt for each Maximum D2H Descriptor Fetch setting is:

• d2h_max_num_desc_fetch_hwtcl = 64 --> [6:0] (7 bits)
• d2h_max_num_desc_fetch_hwtcl = 32 --> [5:0] (6 bits)
• d2h_max_num_desc_fetch_hwtcl = 16 --> [4:0] (5 bits)

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.