Why does the Modelsim® 5.8 SE simulator disappear when I perform a Verilog HDL functional simulation?

Description

The Modelsim 5.8 SE simulator crashes and disappears when you load a Verilog HDL design containing a generate block that refers to a design name (such as the port of a module) that is not declared as a wire type.

As a work around, create a new wire and assign the wire to the design name. In the generate block, refer to this wire.

This problem has been fixed in version 6.0 of the Modelsim simulator.