Why does MAC function with 1000BASE-X/SGMII PCS of Triple Speed Ethernet Intel® FPGA IP detect late collision when it is operating in 10/100-Mbps half-duplex mode?

Description

It is due to the reason that the external third party PHY and cables introduce latency in addition to the latency of the 1000BASE-X/SGMII PCS with embedded PMA. This issue arises when the total latency exceeds the 512-bit slot time as defined in IEEE 802.3 Clause 4.4.

Resolution

The following patch provides a solution to reduce the PCS latency in SGMII mode so the total latency will not exceed the 512-bit slot time.

Please download the appropriate Intel® Quartus® II software version 10.0SP1 patch 1.210 from the following links:

• Intel Quartus II Software version 10.0SP1 patch 1.210 for Window
• Intel Quartus II Software version 10.0SP1 patch 1.210 for Linux
• Intel Quartus II Software version 10.0SP1 ReadMe for patch 1.210

Caution:

You must either have previously installed the Intel Quartus II Software v10.0 SP1 or must install the Intel Quartus II Software v10.0 SP1 before installing this patch. Otherwise, the patch will not be installed correctly and the Intel Quartus II Software will not run properly.

After you install the patch, regenerate your Triple Speed Ethernet Intel® FPGA IP before you compile your design.

OR

Download the appropriate Intel Quartus II Software v10.1SP1 patch 1.77 from the following links:

• Intel Quartus II Software version 10.1SP1 patch 1.77 for Window
• Intel Quartus II Software version 10.1SP1 patch 1.77 for Linux
• Intel Quartus II Software version 10.1SP1 ReadMe for patch 1.77

Caution:

You must either have previously installed the Intel Quartus II Software 10.1 SP1 or must  install the Intel Quartus II Software v10.1 SP1 before installing this patch. Otherwise, the patch will not be installed correctly and the Intel Quartus II Software will not run properly.

After you install the patch, regenerate your Triple Speed Ethernet Intel FPGA IP before you compile your design.