Why does Avalon® streaming data pattern checker IP fail to reset all internal counters and statistics when the RST bit of counter control register is set to 1?

Description

Due to a problem in Embedded Peripherals IP User Guide (UG-01085 | 2019.04.01), it mis-defined the RST bit counter control register as bit[8] in Table 398. Counter Control Field Descriptions.
In fact, the RST bit should be bit[1].
You can reset all counters and statistics by writing bit[1] of counter control register to 1.

Resolution

This problem is fixed starting with Embedded Peripherals IP User Guide version 2020.09.21.