Why do led_char_err and led_disp_err signals of the Arria 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core remain high for one clock cycle when led_link signal becomes high?

Description

When using the Arria® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core, you may see led_char_err and led_disp_err signals remain asserted for one clock cycle after the led_link signal asserts.

Resolution

You can ignore the led_disp_err and led_char_err signals for the first clock cycle after the led_link signal asserts. This is the expected behavior.