Why do I get an error about my generic parameters not being declared when generating my VHDL peripheral in Qsys?

Description

An issue has been identified where VHDL generic parameters do not map correctly for synthesis when connected in Qsys. This issue affects all generic parameters types except for integer. An example error is as follows:

Error: Error (10482): VHDL error at ext_incl.vhd(33): object "\'0\'" is used but not declared File: ...ext_incl.vhd Line: 33

To work around this issue, it is required that all generic parameters in a VHDL Qsys peripheral are of integer type.

This issue shall be resolved in a future release of Qsys.