Why Analysis and Synthesis fails when using multiple variation of same DSP IP core?

Description

You may receive the following error messages if generate multiple variation of same DSP IP core (e.g. CIC, FIR and FFT) in difference directory. This is because all of the QIP files that generated from the same DSP IP core are referring to the same library files but which are stored in difference folders, during the Analysis and Synthesis, Quartus^® II software refer to the QIP file and compile those library files that located at difference folder and which causing the same library files compile twice.   

 

Error (10430): VHDL Primary Unit Declaration error at <file_name>.vhd(12): primary unit " file_name" already exists in library "work"

Resolution

To fix this issue, you can either generate all of the same DSP IP core in the same directory or modify the QIP file to remove the library files.