Warning: Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

Description

Even if timing-driven synthesis is disabled, the Quartus® II software may attempt to initialize the timing netlist if other options such as register retiming are enabled. Initialization of the timing netlist may fail if there are errors in your Synopsys Design Constraint (.sdc) files or if the Quartus II software cannot match identifiers in your .sdc files with nodes in the pre-synthesis netlist. If initialization of the timing netlist fails, the Quartus II software displays the warning:

Warning: Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

If there are errors in your .sdc files, you should correct them to avoid problems during later stages of compilation. If your .sdc files reference nodes that do not exist in the pre-synthesis netlist for your design, either adjust your .sdc files to reference only nodes that exist throughout the compilation process or ignore this warning.