{Name Protected} (/stratixv_atoms.vhd: line 5355, position 21) and verilog parameter being overridden {Name Protected}.{Name Protected} (/stratixv_atoms_ncrypt.v: line -1, position -1) are not type compatible.

You may see this error when simulating a VHDL design in the Cadence NC-Sim software if the VHDL instantiates lower level Verilog HDL files.

To avoid this error, use the -namemap_mixgen option with the ncelab command.

Updated 3 months ago

Version 3.0

Knowledge Base Article