How do I work out the AXI slave ID bit-width for Qsys slave components?

Description

The AXI™ slave ID bit-width is determined by:

maximum_master_id_width_in_the_interconnect log2(number_of_masters_in_the_same_interconnect)

For example:

If an AXI slave connects to three AXI masters and the maximum AXI master ID length of the three masters is 5 bits, the AXI slave ID should be 7 bits:

5 bits 2 bits (log2(3 masters)) = 7