How do I force a signal to use a global clock in VHDL, Verilog HDL, or the Altera® Hardware Description Language (AHDL)?

Description

To force a signal to use a global clock, use the following AHDL function prototype (the port name and order also apply to Verilog HDL): FUNCTION GLOBAL (in) RETURNS (out); VHDL Component Declaration: COMPONENT GLOBAL PORT (a_in : IN STD_LOGIC; a_out: OUT STD_LOGIC); END COMPONENT;

The GLOBAL buffer indicates that a signal must use a global clock, output enable, register control, or memory enable signal. Global signal availability and usage depends on the device family. Refer to the device family data sheets, available on the Altera Literature web page, for specific details.