How do I add files to my project using a TCL commands?

Description

You can add files to your Quartus^® II project using Tcl commands by making the appropriate assignments.

For example, use the following commands to add Verilog HDL files to your project individually:

set_global_assignment -name VERILOG_FILE <filename 1>.v

...

set_global_assignment -name VERILOG_FILE <filename n>.v

File assignment names include VHDL_FILE, VQM_FILE, and BDF_FILE, and others based on the file type to be added.

You can also use a loop to add all design files of a particular type in a directory. For example, use this code sample to add all Verilog HDL files in the current directory to the project:

foreach verilog_file {glob *.v} {

set_global_assignment -name VERILOG_FILE 

}