Have the Stratix® III timing models been updated since the Quartus® II software version 9.0?

Description

Yes, the Stratix® III timing models have been updated in the Quartus® II software version 9.0 SP1 to address the following problems:

Resolution

• Added a clock enable path to the M9K and M144K timing models that were missing in the Quartus II version 9.0 and earlier. 
• Corrected the T4 (DDIO_MUX) timing models  to accurately analyze timing on DDIO output paths. 
• Corrected the write leveling delay chain timing models to eliminate the possibility of hardware functional failures in designs implementing DDR3 interfaces with leveling. 

Related Articles

• Have the Stratix III device timing models for DDIO output delay chains been updated since the release of the Quartus II software version 9.0?
• Have the M9K and M144K device timing models for the Stratix III devices been updated since the release of the Quartus II software version 9.0?
• Have the Stratix III device timing models for DDR3 write leveling delay chains been updated since the release of the Quartus II software version 9.0?