Error: VHDL type mismatch error at <component_name>.vhd: boolean type does not match integer literal

Description

This is a known issue with Qsys v10.1 SP1 and above where a custom component is created with VHDL. When a component is defined having a generic port with its type set to BOOLEAN, Qsys generation passes wrong parameter type in the generated Verilog wrapper.

 

For instance,

 

In ‘my_component.vhd’,

 

entity my_compnent is

generic (

 x: boolean := false;

 ...

 

The generated my_component_hw.tcl would contain the correct type:

set_parameter_property x TYPE BOOLEAN

 

However, the Verilog wrapper file generated by Qsys passes INTEGER type '0' instead of  BOOLEAN type 'false' to x, i.e.

 

my_compnent #(

.x (0),

...

 

To workaround this issue, manually modify the value from "0" to "false" in the Verilog wrapper file. You will also need to modify this file every time you generate the Qsys design.

 

This issue will be fixed in a future release of Quartus® II software.