Do Intel® Cyclone® IV GX devices support single-ended reference clock support in IO Bank 3B and 8B?

Description

Single-ended REFCLK/DIFFCLK positive pins from bank 3B or bank 8B cannot be routed to the FPGA core. This is because no routing path exists between the clock pins and the FPGA core. You will see a fitter error from Quartus®  II software if the above pin assignment is added to the design.

 

 

 

 

Resolution

Single-ended REFCLK/DIFFCLK positive pins can be routed only to MPLL5, MPLL6, MPLL7, and MPLL8 when these PLLs are used for non-transceiver applications.