DMA_afu simulation example pCLK is set at 400 MHz instead of 250 MHz

Description

The out-of-box simulation runs the pCLK at 400MHz, while in the FPGA Interface Manager Data Sheet, the pCLK is set to 250MHz.

Resolution

As ASE is a functional model, changing the pClk frequency won't make performance estimates any more accurate. If the developer still wants to edit the clock’s value, changes need to be made in ASE's rtl/platform.vh in the clock section.