** Error: (vsim-3817) Formal port "altera_reserved_tms" declared in the entity is not in the component

Description

This error occurs in the ModelSim® software for VHDL designs. (Similar errors may occur in other EDA simulation tools).

When the Quartus® II software generates a VHDL gate-level netlist for third-party simulation tools (*.vho) for a design that contains any on-chip debug solution using the JTAG port (such as the SignalTap® II logic analyzer or an SOPC Builder JTAG UART) the netlist contains the following JTAG ports:

• altera_reserved_tms
• altera_reserved_tck
• altera_reserved_tdi
• altera_reserved_ntrst
• altera_reserved_tdo

The error occurs when you simulate the top-level entity with a testbench in a third-party simulation tool if you do not specify these JTAG ports in the top-level component declaration and instantiation.

To avoid this problem, specify the JTAG ports in the component declaration and instantiation of the entity in your testbench as shown below:

COMPONENT <entity name>
 PORT (
       altera_reserved_tms : IN std_logic;
       altera_reserved_tck : IN std_logic;
       altera_reserved_tdi : IN std_logic;
       altera_reserved_ntrst : IN std_logic;
       altera_reserved_tdo : OUT std_logic;
       ...
       );

You can set these altera_reserved* pins to a logic level 0 in your testbench as follows, because you do not drive data on these ports during simulation.

<instance name> : <entity name>
 PORT MAP (
        altera_reserved_tms => '0',
        altera_reserved_tck => '0',
        altera_reserved_tdi => '0',
        altera_reserved_ntrst => '0',
        altera_reserved_tdo => tdo, 
        ...
);