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YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

How to clock the Cyclone 10GX Transceiver Channel for 10GBASE-R

Hi, In “Intel® Cyclone® 10 GX Transceiver PHY User Guide” at page 100, Fig.44, the tx_clkout is 322.265625 Mhz when select PMA bus width of 32 bits (in picture, it says a number for 40 bit wide bus...
YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thank you, Chee Pin so much for your response.

I did try the clock of 156.25MHz to clock the xgmii interfase. It was a little bit worse than the pma_div_clock, which means i got more FE...FE words.

I have no idea how to simulate the transceiver with ModelSim. If you don't mind i can give you my archived design for your further investigation to it.

I am under huge time pressure now about this project and very looking forward to getting your helps .

Thanks again.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

For your information, I have created a simple simulation test design with Native PHY in 10GBaseR mode. In the simulation, I can observe fixed dummy data 64'h0707...07 at the RX parallel output through loopback. Note that this design is just to show the loopback data is similar to the data sent. I am not familiar with 10GBaseR protocol required data. Sorry for the inconvenience.

You may refer to the a.v and a_tb.v in the test_example\mentor folder for top level and test bench. You may ignore the other non-relevant codes in the test bench as this was taken from a different simulation example.

To run the simulation, do the following:

1. Unzip the folder
2. Change the current working directory of Modelsim to test_example\mentor
3. Type "source msim_setup.tcl"
4. Type "ld" to start compilation
5. Type "do wave.do" to populate the waveform
6. Type "run -all" to start the simulation

Please let me know if there is any concern. Thank you.

  • YYang79's avatar
    YYang79
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Thank you, Mr. Chee Pin. I will do.

    Just FYI, and let you know what i have done to my design.

    1)I have used xcvr Toolkit to test my designed hardware. When set serial loopback, It shows PMA stage is working well. It turns out zero BER. So it is definitely something wrong in TX-PCS stage. It cause missing word(64-bit) or FE...FE word.

    2)When i use signaltap monitoring both transmitting and receiving sides they are stable in idle mode meaning i can see stable 0707...07 word. But, when i send out a packet, it sometimes not always, like a 10% chance it loses a word or give a FEFE...FE word.

    Currently i am using 644.53125MHz frequency input to xcvr refence input. Previously i used to use 322.265625MHz. Actually there is no difference.

    I will let you know my simulation results. Thanks a lot for your helps.

  • YYang79's avatar
    YYang79
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi Chee Pin,

    Great news! I found the bugs. As you mentioned, for 10XGBASE-R protocol the writing clock to TX-FIFO MUST be 156.25MHz. I used a pma-div-clock(by2) to drive it. It was wrong. Now my system is working after changed back. Thanks a lot!!!!!

    BTW, in “Intel® Cyclone® 10 GX Transceiver PHY User Guide” at page 100, Fig.44 is correct except the parallel clock should be 322.265625 Mhz for 32bit width bus setting.

    And, on page 102 of the same manual, in the middle paragraph there is a statement,

    ” For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of TX phase compensation FIFO (PCS data) and the write clock of TX phase compensation FIFO (XGMII data in the FPGA fabric).”

    This statement is misleading. "0ppm of the frequency" is not a precise wording.

    Anyway, again, thank you for your help!