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Altera_Forum
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15 years ago

Verilog Compilation Problem: All available logic elements used!

Hi all, I am having a problem compiling my verilog code in Quartus II where all the available logic elements (12'060) are used by the compiler. The code (excerpt) is as follows: begin...
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Altera_Forum
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15 years ago

Sorry, I guess I forgot to add into my post:

reg [15:0] Timings [255:0];

reg [ 7:0] PtrT;

reg TimerFlag;

reg [15:0] contCount;

I think it is the large array that is causing my problem, however I need my device to store a large array and also not use all the logic elements :D is there some code that I need to know in order to store the array in the 239'616 "memory bits" rather than in logic elements?

Dan