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Altera_Forum's avatar
Altera_Forum
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14 years ago

Stratix IV Hold Violations....

... between register A and B. Both Registers are fed by a Global Clock. Source Register and Latch Register are in adjacent labs. The problem seems to be coming from Register A being of type "ALM R...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Nowadays even without LUT_REGs, it's not guaranteed, i.e. the router sometimes has to add delays. By last resort, that doesn't mean you're at 100% of dedicated logic registers, as a lot of them become unavailable as all the inputs might be feeding the LUT before it, for example, or the control signals for the LAB don't match what you need.

I've looked into it, and don't know of anyway to disable LUT_REGs, but the cases I was looking for it was told it would pretty much be a no-fit, so it wasn't a good choice. What does your average and peak routing utilization go betwee(i.e. when having it on and when having it off)? When off, are the hold violations only to/from LUT_REGs?