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Altera_Forum
Honored Contributor
Honored ContributorFixed Point VHDL Support in Quartus
I am asking how people have found the synthesis results with the new VHDL2008 package for fixed point. I have created a design that is a cascaded filter simulating a three phase RL load for a motor c...
Altera_ForumHonored Contributor
Honored ContributorIn contrast to IEEE fixed point package, floating point package is effectively useless for logic synthesis because it's not able to generate any pipelining.
You should use the Altera floating point MegaFunctions instead, they provide al operations you want.
