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Honored Contributor
Honored Contributordifferent width fifo
So i have a Dual clock FIFO with different input and output width. My input is 32bits and my output is 128. I was wondering what would happen if at some point when there is only 32, 64 or 96 bits o...
Altera_ForumHonored Contributor
Honored Contributorthanks guys so i do have underflow protection on. I did some test with singal tap and here is the conclusion i came up with please let me know if it sounds right:
- rdempty get asserted when there is not a full word that can be read. - rdusedw will be at 1 when there is data in the FIFO even tho there is not enough to read a full word - When i read and the FIFO dose not have 128 bits of data it will pad the rest with the last 32 bits that came in
