Most RecentWhat is the <courier>EXTSWITCH</courier> device feature of the Stratix phase-locked loop (PLL) used for?The specified folder is invalid. It contains spaces or illegal characters.Can I use a Cyclone V ES configuration file to program a Cyclone V production device?Why does programming of the non-volatile key fail in Quartus version 15.1 and earlier when AS configuration mode is used in Arria V, Cyclone V and Stratix V devices?Why does the Remote Update IP core not able to read current remote update settings in Intel® Arria® 10 devices?Why do I see errors, or link training or speed change failures, on my Stratix 10 Hard IP for PCIe?Why does “Override MPU Clocks” fail to work in Hard Processor System Agilex™ 5 FPGA IP?Are the RS-FEC Alignment Markers correct when using the 25G Ethernet FPGA IP for Intel® Arria® 10 or Intel® Stratix® 10 devices?Does the Avalon® Memory Mapped Clock Crossing Bridge have support for the "Use synchronous reset" feature in the Intel® Quartus® Prime Software version 18.0?Does the ALTMULT_COMPLEX IP support unsigned operation in V-series and 10-series device families?
