ABerg28
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Re: DE0-NANO Quartus Lite 19.1 NIOS II Project error
The solution is very convoluted. The problem is that with Quartus II version 19.1 and up, WSL was not included. There is a patch, but the patch is too onerous. I would have to install Ubuntu Linux and do some more stuff. I was advised that the best solution was to go back to earlier Quartus II versions before 19.1. I installed 17.1 and it now works fine. I think it would be nice if Intel asked an intern to create a support matrix of Quartus II versions and for each version, list what has improved or changed and what has been removed. And it gets worse. In the download page, Intel suggests that you should always get the latest version, but the page doesn't tell you what the consequences will be if you do. Simple example: All the tutorials discuss how to use Qsys. OK, I'm following along with a tutorial. Where's Qsys? Its not there. Searched the web, nothing. Finally, as a guess, I tried Project Builder. Aha! They renamed Qsys to Project Builder, but apparently kept it a secret. Would it have hurt to put "Project Builder (Qsys)" on the drop down menu? Thanks for your input.1.4KViews0likes0CommentsRe: No response to my plea for help: Try again
I tried your tutorial. I have some comments about it, but I got to the same point as before and got the same error. Your colleague, Boon Beng seemed to identify the source of the error. It seems Quartus version 19.1 and later lacks files. I have to download Unbuntu Linux and then us it to download some Linux files that Eclipse needs, then I need to remember to append .exe to files..... Sigh... Doesn't anybody bother to check this stuff out? I noticed in the tutorial that she was using version 17.1, I was using 19.1. Silly me. It seems to me that it wouldn't be too difficult to develop automated scripts to run your tutorials on each version of Quartus so you could identify incompatibilities before your customers do. Arnie2.2KViews0likes0CommentsRe: No response to my plea for help: Try again
Thank you for pointing this out to me. I think you've correctly identified the problem for me. However, while I appreciate the fact that you apparently solved the problem, I would have appreciated it even more if Intel had made sure that their design tools would actually work in Quartus II version 19.1 for Windows. Arnie Berger2.2KViews0likes0CommentsRe: No response to my plea for help: Try again
Larry, Thank you for your reply. I'll try the course as you suggest. I'm not quite sure what you mean by "redoing the pins." Do you mean because of the differences between the DE-10 and the DE-0, or is it something else? Also, the errors seem to come with trying to create the BSP. Finally, here's some free customer feedback. It would be an incredible help if a fresh pair of eyes looked at the wealth of documents that seems to be available here and reorganized it all, particularly reorganizing around what documents support each version of Quartus and what documents are more general. The technology transfer issues around FPGA design are formidable. Trying to teach it is challenging. Can you send me your direct e-mail in case we need to set up a chat? Thanks. arnie aberger@uw.edu2.2KViews0likes1CommentNo response to my plea for help: Try again
I am trying to run the NIOS II tutorial that will run the Hello World program. I tried to follow a YouTube tutorial and got stuck at the creation of the BSP step. Kept getting error messages that I don't understand. I suspect that the problem may be due to poor video quality or to different Quartus versions. I am running a Terasic DE0-Nano board and using Quartus Lite version 19.1 Can someone point me to a known good, step-by-step tutorial that explains how to build a NIOS II system and is current enough to explain the process on at least the 19.1 version of Quartus? As soon as I see use Qsys I know it is an older version of Quartus, since Qsys has become System Builder. This is for an embedded systems course I want to upgrade. Any help would really be appreciated. Arnie2.3KViews0likes8CommentsDE0-NANO Quartus Lite 19.1 NIOS II Project error
Hello, I'm dead in the water now. I've been following a YouTube tutorial to build a simple adder program to run on the NIOS II in a Cyclone IV on a DE0-NANO board. https://www.youtube.com/watch?v=fjIpzcCmZyY The version of Quartus II he was using was back several versions but it was close enough I could follow it. I was able to get the NIOS II soft core built and downloaded to the board. The problems began when I tried to use the NIOS II - Eclipse software development environment. Do the following steps: 1- Select NEW 2- Select NIOS II Application and BSP from Template 3- Entered the SOPC Information File Name: adder.sopcinfo 4- Entered project name: nios_adder_temp 5- Selected "NEXT" 6- New window popped up. Chose: Create a new BSP based on the application project template 7- Entered Project name:nios_adder_temp_bsp 8- Chose "use default location" 9- Clicked finish 10- Get error message: Failed to execute wsl dos2unix create-this-bsp; ./create-this-bsp --cpu-name nios_2processor --no-make In the Eclipse message window I get this: Executing: wsl dos2unix create-this-bsp; ./create-this-bsp --cpu-name nios2_processor --no-make (D:\UW-Bothell\FPGA-Design\software\nios_adder_temp_bsp) 'wsl' is not recognized as an internal or external command, operable program or batch file. This is where I'm stuck. The YouTube tutorial goes on its merry way. I've watch the tutorial too many times and I'm doing exactly what the tutorial does, but I get stuck here. The Terasic documents or tutorials are too old and are too many Quartus revisons back to be of any use. Any suggestions would be most appreciated. Arnie 7-1.4KViews0likes4CommentsRe: Can't get there from here
Hello AminT, I'm sorry if you didn't understand my post. I have the manual for the DE-1 board. We use them for our teaching. That isn't the issue at all. The issue is how to access the ARM bus inside the Cyclone V FPGA. After doing some research, I found a block diagram that shows why it probably isn't possible to do what I want to do. The reason is that there is a cache sitting between the ARM core and the FPGA fabric. I can write to specific addresses and write through the cache, but that is only to specific addresses. I can't see the bus. Unless there is a way to turn off the cache and bring all bus signals through to the FPGA, I don't see how what I want to do would be possible. Arnie1KViews0likes3CommentsCan't get there from here
We use the Terasic DE-1 Boards for our Digital Electronics class. I would also like to use them for my Embedded Systems class. I would like to be able to do two things: 1- Have the students develop simple peripheral devices in the FPGA fabric, such as timers, buffers or I/O ports and connect them to the ARM core. 2- Bring the bus signals to the GPIO pins so the bus activity could be viewed with an external logic analyzer, Surprisingly, there seems to be disagreement among faculty who teach in this area about whether or not it is possible to do this. My idea scenario is to create buffers that can sit on the address, data and status busses and output to the GPIO pins. Any help would be much appreciated. Arnie1KViews0likes5CommentsBringing HPS bus to GPIO pins
Hello, We would like to use an external logic analyzer with our Terasic DE-1 boards in our undergraduate teaching lab. We would like to bring the HPS bus to the GPIO pins, but I'm not sure how to do that directly, or if we should connect the bus to I/O buffers. Any suggestions would be very appreciated. Arnie1.1KViews0likes1Comment