Semiconductor Engineering Magazine wonders whether Chiplet Technology is Good or Bad. Intel’s answer: Good, Very Good
Mark LaPedus, the Executive Editor for Manufacturing at SemiEngineering.com, recently published an article titled “The Good And Bad Of Chiplets.” From the Intel perspective, there’s only good. LaPedus writes: “With chiplets, the goal is to reduce product development times and costs by integrating pre-developed dies in an IC package. So a chipmaker may have a menu of modular dies, or chiplets, in a library. Chiplets could have different functions at various [manufacturing process] nodes.” LaPedus’ article quotes Ramune Nagisetty, Director of Process and Product Integration at Intel, who discussed the use of chiplet technology at Intel: “We’re in the early stages. More and more products from Intel and our competitors are going to reflect this approach moving forward. Every major foundry has a technology roadmap of increasing the interconnect densities for both the 2.5D and 3D integration approaches. In the coming years, we will see it expand in 2.5D and 3D types of implementations. We will see it expand into logic and memory stacking and logic and logic stacking.” As LaPedus notes in his article, “Intel and a few others have the technologies in place to develop these products.” In fact, Intel® FPGAs have incorporated chiplet technology for years. All members of the Intel® Stratix® 10 GX, SX, TX, and MX FPGA and SoC FPGA families and Intel® Agilex™ FPGA devices use chiplet technology to pair FPGA logic die with I/O tiles. (“Tile” is the name Intel uses for “chiplet.”) These I/O tiles connect to the FPGA die using a chiplet-to-chiplet (or die-to-die) interconnect standard developed by Intel called the Advanced Interface Bus (AIB) and Intel Embedded Multi-die Interconnect Bridge (EMIB) technology, which are both used for heterogeneous semiconductor manufacturing. (Note: Early last year, Intel made use of the AIB standard royalty-free to enable a broad ecosystem of chiplets, design methodologies, service providers, foundries, packaging, and system vendors. DARPA has adopted the AIB standard for its Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program. For details, see “Intel releases royalty-free, high-performance AIB interconnect standard to spur industry’s chiplet adoption and grow the ecosystem.”) In addition to using chiplet manufacturing technology for the I/O functions, the Intel Stratix 10 MX FPGA family uses chiplet manufacturing and packaging technologies to attach high-speed, 3D HBM2 DRAM die stacks to the FPGA fabric die within the FPGA device package, placing several gigabytes of fast memory very close to the FPGA logic. Here, chiplet technology facilitates quick access to data stored in the adjacent HBM2 DRAM stacks. As LaPedus writes, “This is where chiplets fit in. A bigger chip can be broken into smaller pieces and mixed and matched as needed.” LaPedus’ article in Semiconductor Engineering also explains another fundamental reason for the move towards chiplet technology: “…no one technology can meet all needs.” For example, the multiple memory die in an HBM2 die stack are manufactured using a memory-optimized manufacturing process. Memory processes require fewer metal layers than the advanced CMOS processes used for making FPGAs, which reduces the manufacturing cost for the memory. Similarly, I/O functions that must drive long copper traces on circuit boards have functional requirements that diverge from the capabilities of the densest, fastest CMOS logic process available. Here again, the use of chiplet technology makes tremendous sense. Chiplet technology allows the appropriate pairing of function with semiconductor process technology on a case-by-case basis. Rapid product development is yet another important reason for using chiplet technology. The use of tiles (or chiplets) give Intel the ability to reuse proven I/O silicon, which accelerates the product development process by eliminating the need to reimplement, retest, and validate functions that have already been tested and proven in silicon. For example, Intel Agilex devices utilize some of the same I/O tiles developed for and used to manufacture Intel Stratix 10 FPGAs. Intel continues to develop new tiles and to introduce new devices based on these new and existing tiles. Because it’s much easier to design, fabricate, and test a tile rather than an entire FPGA, AIB and tile technology give Intel an express lane for bringing more new products to market faster. Note: For more information, see “Chiplets (tiles) create a high-speed path for getting new FPGAs to market.” You might also be interested in the Intel White Paper titled “Enabling Next-Generation Platforms Using Intel’s 3D System-in-Package Technology.” Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.How Heterogeneous Device Design and Manufacturing Leads to Success
By Patrick Dorsey, Vice President Product Marketing, FPGA and Power Products, Intel The following guest blog is based on remarks by Patrick Dorsey during a panel discussion on “FPGA Hardware Innovations” at the recent The Next FPGA Platform event, held in San Jose, California on January 22, 2020. One of the looming challenges for FPGA hardware design is answering this question: What do you integrate and what do you give up when you integrate? Flexibility matters. FPGA vendors are in the flexibility business. The above question not only matters within the chip, it also matters at the system level. Intel offers many choices to designers of heterogeneous hardware systems. Designers can choose among multiple Intel® Xeon® CPUs. Likewise, they have a choice of several Intel® FPGAs. There’s a lot of value in these choices. Monolithic and heterogeneous integration increase value. Integration in both forms shrinks the overall form factor and improves power consumption. Performance can improve as well. Interfaces can be better optimized. Heterogeneous integration technology enables even more choice. It’s an option at multiple levels within the system. For example, there are a lot of things that we can do with packaging technology, with the interfaces that we have, and with development tools. The options are there. Many things are happening between semiconductor vendors and customers that we can’t talk about publicly. For example, there's a lot of integration that happens with ASICs and with structured ASICs – that’s the Intel® eASIC product. New heterogeneous devices can be manufactured in a customized fashion that could never happen before. Heterogeneous Devices are Here Now Heterogeneous device design and manufacturing is here now. For example, today’s Intel® Agilex™ FPGAs and Intel® Stratix® 10 FPGAs are already heterogeneous FPGAs. We’ve incorporated HBM2 stacked-die DRAM into both types of FPGA. We’ve put the high-speed serial transceivers for these Intel FPGAs on tiles, or chiplets, so that the Ethernet and PCIe protocols are decoupled from the design of the FPGA fabric. The FPGA fabric benefits when moved to new process nodes while interfaces do not. Heterogeneous design allows Intel to innovate in the FPGA fabric and the I/O interfaces separately, and across nodes. We can use multiple nodes to build very complex devices optimally. Another facet is the US government’s involvement with heterogeneous design and manufacturing in these early days. Several DARPA programs are driving research into standalone IP that can sit next to the FPGA. This IP can become chiplets. These chiplets can implement specialized functions in the areas of AI or analog-to-digital converters, for example. The DARPA work is all public. It’s called the CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program. The chiplets concept has advanced very quickly for FPGAs. It’s in volume manufacturing now, as discussed above. However, there are challenges. The first challenge is TDP, thermal design power. The more functions put into the package, the harder it is to get the heat out. So it's primarily a thermal problem but it’s also a business-model problem, which makes it a commercial problem. As soon as you have two or more companies putting their IP into the same device, the business model gets a little more complicated. For example, how you go to market with these mixed-vendor heterogeneous devices? These are some of the challenges for heterogeneous device design and manufacture, but despite these challenges, it's happening now. It Starts with a Great FPGA In terms of the FPGA innovation for heterogeneous device design, it starts with having a great FPGA. All FPGA vendors are trying to build the best FPGA fabric and there are innovations in the ways that the FPGA fabric works. For example, how does the FPGA’s fundamental logic and compute architecture work with memory? One of an FPGA’s key advantages is it’s on-chip memory, which is especially important these days for AI and machine language (ML). For performance reasons, you really want the AI/ML model to fit into the memory in the FPGA package. The next area of innovation is the interconnect, whether it's the heterogeneous interconnect or what happens in the package to solve TDP and power problems. There are things that the US government's doing around the Intel Advanced Interface Bus (AIB), which is an interface that Intel already uses in the Intel Agilex FPGAs and Intel Stratix FPGAs. Intel released the AIB specification into the open-source arena last year and industry organizations like the CHIPS Alliance are pushing the AIB specification as an open industry standard to allow better die-to-die connectivity and to jumpstart the chiplet ecosystem. This may sound funny coming from Intel, but it's not about the semiconductor process alone. Don’t misunderstand that statement. Process technology is extremely important and Intel continues to drive the Moore’s Law process technology cadence. So being on the latest process node is important and I think you'll see FPGAs continuing to lead the charge when it comes to process technology. However, the choices made in the design of a new device really depend on the problems you're trying to solve. You only need to take some functions to the most advanced process node. Some functions, especially I/O functions, can't take advantage of the most advanced process node. Analog functions and memory can’t use the most advanced process nodes. This is where heterogeneous device design and manufacturing shines. Chiplets and heterogeneous devices enable choices. You can choose to advance only the functions that need to go faster while reusing designs that already meet performance and power requirements. Heterogeneous design allows you to make different design tradeoffs – in terms of static power, for example – and power has become critical in the design of every new device. At Intel, we're constantly trying to balance power and performance. Process nodes matter and a mix of process nodes gives you the most design choices by allowing an easy mix of custom IP, standard IP, flexible FPGA IP, and interconnect IP. Heterogeneous design and manufacturing allow Intel to decide how to best mix these technologies to create new semiconductor products. The world's getting more complicated, but Intel has more ways to solve these problems than ever before. Legal Notices and Disclaimers: Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. 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