Accelerate NFVi Workloads For 5G Deployments Webinar: Watch On-Demand Now
The recently-held “Accelerate NFVi Workloads For 5G Deployments” webinar highlights the collaboration between Juniper Networks, HCL Technologies, and Intel® to solve network performance challenges and allow Contrail users to experience increased overall server performance and utilization for vRouter-based infrastructures in telecommunications environments.
Open vSwitch for NFVi based on Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 achieves first-packet learning rate of 500K rules/sec, near-wireline performance
As the numbers of subscribers, competitors, and technology advances grow, communications service providers (CoSPs) need to differentiate their products and services while keeping improved power efficiency and the need to control total cost of ownership (TCO) as ever-present goals. Intel and HCL have addressed these challenges with a joint solution that combines Intel® hardware and HCL software. HCL has created a solution using the Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 that can dramatically increase network functions virtualization infrastructure (NFVi) routing and switching performance while preserving flexibility. The resulting solution, the Open vSwitch (OvS), is a production quality, multilayer virtual switch that can implement software-defined networking (SDN), which is crucial to creating a closed-loop, fully automated NFVi solution. The OvS can either forward packets through a kernel-based datapath or by using the Linux Data Plane Development Kit (DPDK). Aggressive software optimization offloads NFVi forwarding tasks to the Intel FPGA PAC N3000, yielding the following preliminary results 1 : For more details, see the new Solution Brief titled “Increase NFVi Performance and Flexibility.” (Click on the link to download the Solution Brief.) Notices and Disclaimers 1 Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intc.com. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Hardware Acceleration and Segment Routing over IPv6 (SRv6) help CoSPs Optimize and Simplify their Networks
Communications service providers (CoSPs) are seeking ways to differentiate themselves and to enhance their customers’ experiences in the fast-evolving telecommunication (telco) market—all while keeping costs under control. Exponential traffic growth and constant pressure to add more services and subscribers can tax legacy infrastructure, forcing CoSPs to constantly optimize and simplify their networks. Many CoSPs have deployed network functions virtualization (NFV) in an effort to optimize their networks. However, an influx of new subscribers and growing data loads consume a growing number of CPU cycles simply to route traffic, which leaves fewer compute resources to run actual containerized network functions (CNFs) and virtualized network functions (VNFs) that CoSPs want to support. The end result: suboptimal performance and the need for more hosts. To help overcome these challenges, CoSPs are turning to technologies such as hardware acceleration and segment routing over IPv6 (SRv6). SRv6 helps address the requirements of NFV and software-defined networking (SDN) architecture. It provides a unified solution for networking programmability, service function chaining (SFC), protocol simplification, traffic engineering, and mobile and fixed network convergence. An SRv6 solution from Intel and HCL overcomes network bottlenecks and achieves up to 3x savings in processor cores by offloading low-level SRv6 processing to the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000. The card is reprogrammable and delivers the flexibility that CoSPs need to support new networking workloads. HCL has built an optimized architecture that enhances network throughput and predictability while reducing latency by taking advantage of the plugin-based framework of vector packet processing (VPP) and by offloading CPU-intensive operations to the Intel FPGA PAC N3000. The solution frees up CPU cores by offloading CPU-intensive segment-routing functions to the Intel FPGA PAC N3000, which means that four CPU cores in the hardware-assisted solution can deliver comparable performance to 12 cores running a software-based SRv6. That’s a 3x savings in CPU cores as shown in the graphic below. 1 Freed CPU cores and cycles can be dedicated to vital CNF workloads running on that networking infrastructure instead of networking infrastructure. The solution’s small footprint can help reduce power and cooling costs. It is available for both VNF-based environments through VPP support and CNF-based environments (and Kubernetes) through Contiv-VPP support. The HCL solution based on the Intel FPGA PAC N3000 supports the following SRv6 endpoint behaviors, all of which enable SFC, L2VPN, and L3VPN: Static proxy (End.AS) Dynamic proxy (End.AD) Decapsulation and cross-connect (End.DX) Decapsulation and specific table lookup (End.DT) For more technical details, see the new Solution Brief titled “Accelerate SRv6 Processing.” (Click on the link to download the Solution Brief.) Notices and Disclaimers 1 Based on HCL testing on January 21, 2020. Test environment configuration: Intel® Xeon® Platinum 8180M processor (2.50 GHz, 56 cores), CentOS 7.6, kernel 3.10.957, Contiv-VPP v3.3.2.1 (VPP 19.08), Data Plane Development Kit (DPDK) v19.05, Ixia Network Tester, Intel FPGA PAC N3000, with up to four virtual machines (VMs) running L3 Forwarding; test topology: traffic generator connected back-to-back to the server host through optical cables. QSFP28 100 Gb port is broken out into 4 x 25 Gb; only two of them are used. For more information about testing, contact HCL. Performance results are based on testing as January 21, 2020, and may not reflect all publicly available security updates. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit intel.com/benchmarks. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at intel.com. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.F5 Networks BIG-IP VE for SmartNICs uses Intel® FPGA Programmable Acceleration Card N3000 to efficiently block incoming DDoS attacks in cloud environments while lowering TCO
Tom Atkins, a Product Marketing Manager at F5 Networks, has just published a blog that describes the company’s fully integrated BIG-IP Virtual Edition (VE) solution, which efficiently blocks incoming Distributed Denial of Service (DDoS) attacks in cloud environments using hardware acceleration to realize significant performance and total cost of ownership (TCO) gains. The solution consists of the F5 Networks BIG-IP AFM (Advanced Firewall Manager) Virtual Edition integrated with the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 SmartNIC. In his blog, Atkins says that the combination of the F5 Networks BIG-IP AFM and the Intel FPGA PAC N3000 SmartNIC frees up CPU cycles for other functions and improves overall DDoS mitigation capacity. The result: The F5 Networks BIG-IP VE solution can handle DDoS attacks as much as 300X larger than software-only implementations while reducing TCO by approximately 47% by migrating CPU-intensive DDoS mitigation tasks including network threat intelligence, machine learning, packet-based analysis and white listing to the SmartNIC, which frees up high-value CPU cores to run revenue-generating cloud applications instead. For more information, read Atkins’ blog titled “Mitigate DDoS Attacks up to 300x Greater in Magnitude in Cloud Environments: Introducing BIG-IP VE for SmartNICs,” and then watch the associated 10-minute video from F5 Networks titled “Boosting BIG-IP VE Performance with Hardware Acceleration Technologies.” The video features F5 Networks Senior Strategic Architect Jason Rahm, who delves even further into the technical details of this topic. (Note: In the video, Rahm states that the F5 Networks BIG-IP AFM VE solution with the Intel® FPGA PAC N3000 SmartNIC delivers a 70X performance boost over a software-only implementation, but a footnote in the video’s description states that more recent testing has yielded performance improvements as large as 300X.) Also, please see the associated Solution Brief titled “High Capacity DDoS Protection in Cloud Environments with F5 BIG-IP VE for SmartNICs and Intel FPGA PAC N3000.” For more information about the Intel FPGA PAC N3000, click here. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. SmartNICs based on Intel® FPGAs Boost Converged Broadband Network Performance
To meet consumer demands, telco providers that offer both wireless and wireline access to customers rely on dual, complex fixed and mobile infrastructures that must constantly be upgraded and maintained at great cost. Consequently, telco Internet providers continuously explore new ways to reduce costs and create new revenue streams. Many operators, for example, are eyeing 5G fixed-mobile convergence (FMC) to lower costs and add new agile services. FMC also helps telco providers to meet the customer needs. Both consumer and business customers are looking for multi-access connectivity and a seamless service experience. Innovations such as software-defined networking (SDN) and network function virtualization (NFV), are key to enabling the network transformation at the telco’s edge. These innovations support new capabilities including the User Plane Function (UPF), the Access Gateway Function (AGF), and Broadband Network Gateway (BNG). The combination of these new capabilities enables higher throughput and lower latency for traffic between the telco central office (CO) and broadband customers, both wireless and wireline, through a newly shared infrastructure. Finding the right hardware on which to host these new virtual network functions (VNFs) at the network edge is a big challenge because telco COs must upgrade infrastructure while meeting physical space, power, and cooling constraints. The hardware solution also must be sufficiently cost-effective to support the additional, ever present goals for reducing capital expenditures (CapEx) and operating expenses (OpEx). Finally, the solution needs to scale to handle tens of thousands―or even hundreds of thousands―of subscriber connections. SmartNICs built with Intel® FPGAs provide solutions to these challenges while still offering the advantages of a commercial off-the-shelf (COTS) solution. One such SmartNIC, just announced by Silicom, is the Silicom FPGA SmartNIC N5010. This SmartNIC is a high-performance, programmable PCIe server adapter that combines an Intel Stratix 10 DX FPGA – which integrates high performance, high-bandwidth memory (HBM) – and an Intel® Ethernet 800 series adapter. Use these SmartNICs to accelerate the UPF, AGF, and BNG functions and to realize many performance benefits including high-throughput packet processing, smart and effective packet load balancing to CPU cores, and Hierarchical Quality of Service (HQoS). These capabilities are crucial to support high bandwidth and low latency in converged access networks. A new Solution Brief from Intel titled “SmartNICs with Intel® FPGAs Boost Performance for Converged Broadband Networks” discusses these topics in more detail. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Build efficient 5G and 4G telecom offload functions quickly using Netcope Technologies’ P4 service and Intel® FPGA Programmable Acceleration Cards
Smart Network Interface Cards (SmartNICs) can boost performance in mobile telecom networks. For 4G networks, SmartNICs can be used to implement many network functions in virtual machines or containers rather than using dedicated hardware, resulting in better performance and more network flexibility. Meanwhile, 5G networks will demand even more performance and flexibility, and SmartNICs can meet these goals. An Intel® FPGA Programmable Acceleration Card (PAC) N3000 – a full-duplex 100 Gbps in-system re-programmable acceleration card for multi-workload networking application acceleration – can offload telecom network server CPUs, which reduces the total number of required servers and cuts both capital and operational expenses. A new Intel White Paper titled “Making Virtualized Mobile Gateways More Efficient,” written in conjunction with Netcope Technologies – a Gold member of the Intel® FPGA Partner Program – discusses the use of the open-source P4 network programming language in conjunction with Netcope’s P4 service to quickly develop and deploy offload cores that accelerate networking functions. The offloaded networking functions are often straightforward but require significant compute performance, which makes them ideal for conversion to an FPGA-based IP core using the P4 language. Examples of such functions include Network Address Translation (NAT), Deep Packet Inspection (DPI), and content-specific processing optimizations for Web and video traffic. Using P4 to describe these functions rather than traditional FPGA programming languages including VHDL and Verilog can reduce development time for these functions from weeks to days. In addition, FPGA-specific design knowledge is often not required to develop these functions using P4. For more details, click here to download this new Intel White Paper. For more information about the Netcope implementation of P4 used with Intel® FPGAs, see “Develop custom 200 Gbps packet-processing pipelines using Netcope P4 for SmartNICs based on Intel® Stratix® 10 FPGAs.” Legal Notices and Disclaimers: Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Altera is a trademark of Intel Corporation or its subsidiaries. Cyclone is a trademark of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Accenture, the Sulubaaï Environmental Foundation, and Intel partner to create the CORaiL underwater vision system to help restore fragile coral reef ecosystems
Accenture has partnered with the Sulubaaï Environmental Foundation and Intel to develop an innovative solution for recreating and restoring coral reefs to their former health by installing special equipment including underwater cameras in the Pangatalan Island marine protected area in the Philippines. This system supports the Sulubaaï Environmental Foundation’s efforts to regrow and rebuild the island’s coral reef ecosystem. Coral reefs are one of the most diverse ecosystems on planet Earth and they’re threatened by a host of challenges including overfishing, deteriorating water quality, and ocean pollution. The project is called CORaiL, where the “ai” stands for “artificial intelligence.” The engineering solution combines mobile, digital, and deep learning technologies. By employing rapid-prototyping techniques, the engineering team quickly developed an edge computing solution to monitor the progress of the restoration efforts by observing, classifying, and measuring marine life activity in the coral reef. The CORaiL testbed was initially launched in May, 2019. Coral reef restoration efforts in the Pangatalan marine protected area involve the installation of concrete structures on the sea bottom. These structures serve as scaffolds that anchor new fragments of living coral. The CORaiL system studies these living coral fragments as they grow over time. As the coral reef grows, it creates a larger and larger haven for marine life. Consequently, the CORaiL system also monitors the presence of fish. An artificial, concrete reef to provide support for unstable coral fragments underwater is implemented by Accenture, Intel and Sulubaaï Environmental Foundation in the coral reef surrounding the Pangatalan Island in the Philippines. Photo Credit: Accenture Smart underwater video cameras located near the concrete scaffolds employ Accenture’s Video Analytics Services Platform (VASP), which provides a toolset for rapidly building and deploying AI capabilities. Accenture’s VASP provides multiple powerful analytics and visualization tools to help analysts increase operational insight and timely decisions from computer vision models. VASP is powered by multiple Intel technologies including Intel® Xeon® CPUs, Intel® FPGA Programmable Acceleration Cards (PACs), and the Intel® Neural Compute Stick 2 powered by the Intel® Movidius™ Myriad™ X Vision Processing Unit (VPU) and the Intel® Distribution of OpenVINO™ toolkit. The resulting platform provides an effective, non-invasive observation platform for ongoing observations. The underwater cameras detect and photograph fish as they swim past. Deep learning algorithms built into the cameras then count and classify the fish. The processed data then travels wirelessly to the ocean surface and then to onshore servers where it’s processed, analyzed, and stored. The resulting data and reports allow the research team to make data-driven decisions about the restoration work. Accenture hopes to use this system for other marine applications including fish migration studies and intrusion-detection and -monitoring of restricted underwater areas such as marine sanctuaries and fish farms. For more information, see “Using Artificial Intelligence to Save Coral Reefs.” For more information about the Accenture VASP system, click here. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.FPGA-based reference design from Algo-Logic and Intel cuts high-speed financial trading latency by 3.8X
Algo-Logic and Intel have developed a high-speed reference framework design that offloads the network stack required for high-speed financial trading to logic instantiated in an Intel® Stratix® 10 FPGA on the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) D5005 platform. The reference design includes: A fast PCIe interface (the Algo-Logic Fast Data Mover) A C/C++ to FPGA business logic implementation area that serves as a target for logic developed using high level synthesis (HLS) A TCP/IP offload engine An ultra-low-latency (ULL) 10GbE media access control (MAC) According to the conclusion in a new White Paper titled “Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005,” the reference design achieves 3.8X lower latency compared to a design with just an Ethernet offload engine. 1 These innovations significantly accelerate low-latency trading system development while offering the flexibility to add proprietary trading algorithms to the FPGA. Click on the link above for more technical details. Notices & Disclaimers 1. Testing by Algo-Logic on October 26, 2020. Server configuration: HPE DL380 G10, CPU = Intel® Xeon® Gold processor 6154 @ 3.00 GHz; DRAM = 128 GB total, and RHEL* 7.6. Production Intel FPGA PAC D5005. For more information, a benchmark report is available under NDA. Contact your sales rep for more information. Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Financial Times article discusses Sulubaaï Environmental Foundation’s efforts to save coral reefs using smart underwater cameras and AI
Last week, the Financial Times published an article by Adam Green titled “Tech knowhow gives new lease of life to marine habitats.” The article discusses various efforts underway to combat the demise of sensitive marine ecosystems, especially coral reefs, and the first project discussed is the Sulubaaï Environmental Foundation’s efforts to regrow and rebuild Pangatalan Island’s marine protected area in the Philippines. This project, done on conjunction with Accenture and Intel, has developed an innovative solution for recreating and restoring the island’s coral reefs to their former health that includes the addition of AI capabilities to underwater cameras that automatically capture and process tens of thousands of images of fish and other marine species to identify and monitor their migration patterns and their daily life in the reef. The Financial Times article quotes Patrick Dorsey, a Vice President in the Intel Programmable Solutions Group, who discusses the reasoning behind the creation of the automated camera system, which is both more accurate and less disruptive than human divers when used to catalog ongoing changes to the reef’s marine life. The smart underwater video cameras employ Accenture’s Video Analytics Services Platform (VASP), which provides a toolset for rapidly building and deploying AI capabilities. Accenture’s smart underwater video cameras located near the concrete scaffolds employ Accenture’s VASP, which is powered by multiple Intel technologies including Intel® Xeon® CPUs, Intel® FPGA Programmable Acceleration Cards (PACs), and the Intel® Neural Compute Stick 2 powered by the Intel® Movidius™ Myriad™ X Vision Processing Unit (VPU) and the Intel® Distribution of OpenVINO™ toolkit. For more information about the technology behind this project, see “Accenture, the Sulubaaï Environmental Foundation, and Intel partner to create the CORaiL underwater vision system to help restore fragile coral reef ecosystems.” Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Flumaion accelerates quantitative financial calculations for high-frequency trading with Intel® PAC with Intel® Arria® 10 GX FPGA and InAccel Orchestrator
Financial workloads must pore through and process huge data sets. For high-frequency trading and risk management applications, the software demands are both time- and resource-intensive. The computing hardware must keep pace with these demands and must continuously shift industry parameters because financial markets can change direction in an instant. Failure to track a market closely results in expensive trading losses. Hardware accelerators speed algorithm execution and offer significant acceleration for financial applications. An example financial workload is back testing, which tests a simulated trading series on reliable historical data. Back testing is a computationally intensive task because of the sheer volume of data. Hardware accelerators based on FPGAs can offer significant performance improvements for financial workloads, which is why Flumaion harnessed the power of the Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA to speed quantitative finance applications. Flumaion also employed InAccel’s orchestrator, which enables easy deployment, scaling, resource management, and task scheduling for FPGA-based acceleration of financial applications. High-level design languages such as OpenCL™, C++, and Data Parallel C++ (part of the Intel® oneAPI initiative) simplify the transition from software programming to FPGA programming. FPGA Acceleration Libraries (FAL) ease a software developer’s FPGA programming experience by providing highly optimized, common functions that are more easily integrated with the developer’s code. The Intel® FAL includes more than 350 functions including linear algebra, statistics, random numbers, date utilities, and options pricing. The Intel FAL also includes pre-compiled FPGA binary files for commonly used financial algorithms such as Black-Scholes, binomial pricing, quadrature integration, partial differential equation solving, and Monte Carlo. The InAccel Coral manager further abstracts the resources available in a cluster of Intel FPGA PACs, simplifying deployment of one or more applications across multiple FPGAs. InAccel’s manager schedules, dispatches, and manages the accelerated functions. It also balances workloads among the available resources in the Intel FPGA PAC cluster. It manages and configures the accelerator cards as well. InAccel’s orchestrator is fully compatible with the Intel FAL and Intel FPGA PAC cards. InAccel’s repository of precompiled FPGA bitstreams for Intel FPGAs using Intel library functions allows software developers to more easily use hardware accelerators like the Intel® PAC with Intel® Arria® 10 GX FPGA cards. Flumaion applied its expertise in financial risk analytics, mathematical modeling, and C++ coding experience to harness the performance of the Intel PAC with Intel® Arria® 10 GX FPGA and the productivity enhancements of InAccel tools when developing a quantitative financial modeling testbench. The company then applied a test suite consisting of ten test files to this testbench. Each test file consisted of 3.4 million rows of equity option trades coded in the JSon format. The testbench transforms the JSon files into matrices appropriately formatted for the Intel PAC with Intel® Arria® 10 GX FPGA and then uses the InAccel API to load the matrices into the FPGAs and then to run the workloads. A new Solution Brief titled “Accelerating Quantitative Finance with FPGA-Based Acceleration Cards” describes the results of these tests, which demonstrate a performance improvement of as much as 3.3X when compared to a system with dual Intel® Xeon® Platinum 8160M processors (24 cores each) running Quantlib. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers The configuration used for both the Quantlib results and the Intel® FAL/InAccel solution comprises Dual Intel® Xeon® Platinum 8160M processors, 384 GB of RAM at 2666 MHz, 375 GB of Intel® Optane™ P4800x persistent memory storage, and two Intel® PAC with Intel® Arria® 10 GX FPGA cards. Intel® technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel® microprocessors. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
