Can the new Intel® eASIC™ devices help you reach your 4G and 5G equipment design goals?
By Ronnie Vasishsta, VP and GM, Intel Corporation There is a lot of discussion in the industry today surrounding 5G telecommunications and networking. I even see television commercials about 5G popping up more and more. What's lost in all the excitement about 5G is that the 4G and 4G Advanced Pro standards are still in the deployment phase – and the equipment is still evolving. Many current telecom and networking use cases can be met with these existing 4G solutions and they serve as a bridge to 5G. As a result, vendors are now developing flexible equipment that can implement 4G standards now, with an eye towards reconfiguring them to 5G later. What 5G adds is not just new technologies but also new business models. Yes, 5G offers enhanced speed on mobile broadband, but the 5G technologies also add some new use cases. For example, some of these new use cases take advantage of new 5G capabilities such as massive machine-to-machine communications that are being used to facilitate smart factories, autonomous driving, enhanced video analytics, more accurate location tracking and a plethora of others. So 5G brings new capabilities, new use cases, and enhanced speed to the networking and telecom markets. Because these generational transitions from 4G to 5G are happening so quickly, and because 4G itself is evolving with new technologies such as massive MIMO, millimeter wave, beamforming, and carrier aggregation, it’s very hard for 4G and 5G equipment vendors to work with a fixed set of hardware solutions. Equipment vendors’ customers are looking for adaptable, configurable solutions to meet the changing needs of their customers. These solutions often must not only be software-configurable; they must take advantage of configurable hardware – meaning reconfigurable silicon – to meet some of the new technology latency, performance, power and cost requirements of these increasingly advanced networks. Intel is ideally situated to aid equipment vendors and their customers with this transformation as various 4G deployments and 5G standards are released. Intel software- and hardware-programmable products allow customers to accommodate the constant need for network reconfiguration while still maintaining performance, power, and cost targets. For these 4G and 5G applications, Intel® Xeon® CPUs, Intel® FPGAs, Intel® eASIC™ devices, and Intel® ASICs are very complementary products. Intel FPGAs can very efficiently implement certain functions within specific telecom and networking standards while offering benefits in terms of performance and cost. These FPGAs give equipment makers the option to quickly accelerate network functionality to an Intel FPGA sitting immediately adjacent to the Intel Xeon CPU. This migration option is especially attractive when Intel Xeon CPU cycles can better be used for revenue-generating tasks rather than for lower-level tasks. More efficiencies can be gained by moving the offloaded functions from the Intel FPGA to an Intel eASIC structured ASIC as designs mature and as feature sets solidify. Intel eASIC devices allow reuse of IP from FPGA-based designs and can cut power consumption by as much as 50% at the same clock frequency relative to the same designs implemented in FPGAs while also lowering unit costs. In addition, developing a design using an Intel eASIC device requires only half of the time needed to develop an ASIC with similar capabilities. The broad offering of Intel Xeon CPUs, Intel FPGAs, Intel eASIC devices, and Intel ASICs really gives equipment vendors the ability to carefully manage their product life cycles as their designs pass through various product phases from prototypes, to early production, to mature production volumes. Intel has introduced the next generation of Intel eASIC devices, code-named Diamond Mesa. These new Intel eASIC Diamond Mesa devices will consume less power and will be faster than the existing Intel eASIC N3XS products. In addition, these new Intel eASIC Diamond Mesa devices incorporate a multicore, embedded, hard processor subsystem, which means that these devices can implement control functions as well as well as many DSP and networking functions on a single device. The hard processor subsystem incorporated into the Intel eASIC Diamond Mesa devices allows the identical software to operate on both the new Intel® Agilex™ SoCs and the Intel eASIC Diamond Mesa devices. Structured ASICs like Diamond Mesa balance the configurability and fast time-to-market of FPGAs with the power-efficient, purpose-built performance of custom ASICs, and are a key piece of Intel’s 5G solution portfolio. Software and hardware portability across devices is a hallmark of Intel FPGAs and Intel eASIC devices. Significant know-how developed over many years permits Intel to migrate FPGA-based designs into an Intel eASIC structured ASIC quickly and easily while reusing much of the IP. In addition, Intel is moving some of the migration work to automated tools, which makes the process even faster and easier. However, your design need not target an Intel FPGA for easy migration to an Intel eASIC device. Intel has developed techniques to migrate designs from any vendor’s FPGA into Intel eASIC structured ASICs. Some customers that are familiar with Intel eASIC structured ASIC devices already target these devices directly for specific end products without ever targeting an FPGA. (Or, perhaps the FPGA is used for prototyping, in preparation for a conversion to an Intel eASIC device.) In such cases, a tool flow called eTools, which combines several in-house hardware development tools created by Intel, eases migration and helps customers implement their designs directly in the Intel eASIC fabric. It’s also possible to migrate from an eASIC device to a full-mask-set ASIC should the project’s power or unit-cost goals require it. Networking and telecom equipment OEMs and companies building out 4G and 5G infrastructure networks should review the full line of Intel semiconductor and IP products in the light of their cost and power targets to determine how to best take advantage of the full breadth of the unique Intel device offerings. These products help equipment vendors put multiple products with the right bill of materials and the right price point into the market quickly for those with limited R&D budgets. Legal Notices and Disclaimers: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com. 2X Higher Performance or 50% Lower Power based on circuit simulations for the same function performed September 2019. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configuration details and may not reflect all publicly available security updates. No product or component can be absolutely secure. Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. 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The Intel® eASIC™ N5X structured ASIC is the industry's newest and most capable structured ASIC family. This product cuts power consumption and achieves higher performance relative to FPGAs, and ultimately enables faster TTM relative to ASICs. Intel eASIC N5X devices are the first structured ASICs from Intel that leverage Intel innovations such as the hard processor system and security features derived from and compatible with the Intel Agilex FPGA. Security features in the Intel eASIC N5X structured ASIC family include the secure device manager used in Intel Agilex FPGAs, which manages boot, authentication, and anti-tamper features. Core power consumption for Intel eASIC N5X devices is as much as 50% lower than for Intel Agilex FPGA devices, which eases thermal constraints and allows designers to increase performance in the same thermal envelope. When compared to ASICs, Intel eASIC N5X devices lower total cost of ownership by delivering faster TTM and lower NRE. This new product family targets a broad range of workloads including 5G wireless base stations and radios, cloud acceleration, storage, AI inference processing, and many edge applications. These Intel eASIC N5X structured ASICs leverage the Diamond Mesa SOC technology discussed at Mobile World Congress earlier this year. (See “Can the new Intel® eASIC™ devices help you reach your 4G and 5G equipment design goals?”) For more information about the Intel eASIC N5X structured ASIC family, see the associated Intel News Byte and click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel and DARPA announce SAHARA program to develop secure, reliable, domestic source of Structured ASICs
Intel and the U.S. Defense Advanced Research Projects Agency (DARPA) have just announced a three-year partnership to advance the development of domestically manufactured structured ASIC platforms through a partnership program named “Structured Array Hardware for Automatically Realized Applications” (SAHARA). The SAHARA program’s goal is to enable the design of custom chips that include state-of-the-art security countermeasure technologies, made available through a reliable, secure, domestic source of leading-edge semiconductors. As the sole U.S.-based manufacturer of advanced semiconductors, Intel will provide supply-chain security to the SAHARA partnership through manufacturing, assembly, and test facilities located in the U.S. The company currently offers several Intel® eASIC structured ASIC device families. “We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process,” said José Roberto Alvarez, senior director of the CTO Office in the Intel Programmable Solutions Group. Intel will collaborate with collaboration with the University of Florida, Texas A&M and University of Maryland to improve the security of these structured ASICs through the entire design/verify/test/manufacture cycle. Intel will develop security countermeasure technologies to enhance protection of data and intellectual property against reverse engineering and counterfeiting. Meanwhile, the university teams will employ rigorous verification and validation techniques and will develop new attack strategies to test the security of these devices. These security countermeasure technologies will then be integrated into Intel’s structured ASIC design flow. For more information about the SAHARA program announcement, see “Intel, DARPA Develop Secure Structured ASIC Chips Made in the US”. For more information about Intel eASIC N5X devices, see “The Intel® eASIC™ Diamond Mesa Structured ASIC technology now has a name: Intel eASIC N5X”. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Free Aerospace and Defense Electronics Design Webinar from Arrow and Intel – November 5. Register now
If your team is working on next-generation aerospace or defense projects, then a new Webinar from Arrow and Intel titled “Delivering Next Generation Aerospace & Defense solutions with Intel Technologies” might just bring you some information you can use, immediately. Intel has unique offerings for the most demanding aerospace and defense electronic designs. For example, Intel is the only semiconductor vendor in the world to offer a custom logic portfolio that spans Intel® FPGAs including the new Intel® Agilex™ FPGA family, Intel® eASIC™ structured ASICs, and full-custom ASICs. This logic continuum allows your team to choose exactly the right semiconductor implementation technology for every stage in your project – from development and initial testing, to prototyping, deployment, and maintenance. Key agenda topics for this Webinar include: The Intel Microelectronics Assurance Strategy for the US Government The US-based Intel custom ASIC foundry Bridging the gap between Intel FPGAs and ASICs with Intel eASIC structured ASICs Intel reference designs for military applications such as electronic warfare (EW) and radar Intel Agilex FPGA technology Device security and anti-tamper features for aerospace and defense applications The Webinar will be held on November 5, 2020 at 14:00 GMT. For more information about the Webinar including the full event agenda and registration, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.