/ {
//arch/arm/boot/dts/socfpga_arria10.dtsi
...
    soc {
...
		fpga_mgr: fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100
			       0xffcfe400 0x20>;
			clocks = <&l4_mp_clk>;
			resets = <&rst FPGAMGR_RESET>;
			reset-names = "fpgamgr";
		};

+		fpga_bridge0: fpga-bridge@ff200000 {
+			compatible = "altr,socfpga-lwhps2fpga-bridge";
+			reg = <0xff200000 0x100000>;
+			resets = <&rst LWHPS2FPGA_RESET>;
+			clocks = <&l4_main_clk>;
+			bridge-enable = <1>;

			//linux-socfpga.a9/Documentation/devicetree/bindings/fpga/fpga-region.txt
+			#address-cells = <1>;			#size-cells = <1>;
+			ranges;
+
+			fpga_region0: fpga-region0 {
+				compatible = "fpga-region";
+				fpga-mgr = <&fpga_mgr>;
+
+				// linux-socfpga.a9/Documentation/devicetree/bindings/fpga/fpga-region.txt, Required properties:
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+			};
+		};

+		// linux-socfpga.a9/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
+		fpga_bridge1: fpga-bridge@c0000000 {
+			compatible = "altr,socfpga-hps2fpga-bridge";
+			reg = <0xc0000000 0x10000>;
+			resets = <&rst HPS2FPGA_RESET>;
+			clocks = <&l4_main_clk>;
+			bridge-enable = <0>;
+		};
...
    };
...
};