// avlm_avls_1x1.v // Generated using ACDS version 21.1 842 `timescale 1 ps / 1 ps module avlm_avls_1x1 ( input wire clk_clk, // clk.clk output wire laser_laser_current, // laser.laser_current output wire laser_laser_pulse, // .laser_pulse output wire laser_laser_shunt, // .laser_shunt input wire reset_reset_n // reset.reset_n ); wire [31:0] master_0_m0_readdata; // mm_interconnect_0:master_0_m0_readdata -> master_0:avm_readdata wire master_0_m0_waitrequest; // mm_interconnect_0:master_0_m0_waitrequest -> master_0:avm_waitrequest wire [31:0] master_0_m0_address; // master_0:avm_address -> mm_interconnect_0:master_0_m0_address wire master_0_m0_read; // master_0:avm_read -> mm_interconnect_0:master_0_m0_read wire [3:0] master_0_m0_byteenable; // master_0:avm_byteenable -> mm_interconnect_0:master_0_m0_byteenable wire master_0_m0_readdatavalid; // mm_interconnect_0:master_0_m0_readdatavalid -> master_0:avm_readdatavalid wire [31:0] master_0_m0_writedata; // master_0:avm_writedata -> mm_interconnect_0:master_0_m0_writedata wire master_0_m0_write; // master_0:avm_write -> mm_interconnect_0:master_0_m0_write wire [2:0] master_0_m0_burstcount; // master_0:avm_burstcount -> mm_interconnect_0:master_0_m0_burstcount wire [7:0] mm_interconnect_0_slave_0_avalon_slave_0_readdata; // slave_0:avs_readdata -> mm_interconnect_0:slave_0_avalon_slave_0_readdata wire mm_interconnect_0_slave_0_avalon_slave_0_waitrequest; // slave_0:avs_waitrequest -> mm_interconnect_0:slave_0_avalon_slave_0_waitrequest wire [7:0] mm_interconnect_0_slave_0_avalon_slave_0_address; // mm_interconnect_0:slave_0_avalon_slave_0_address -> slave_0:avs_address wire mm_interconnect_0_slave_0_avalon_slave_0_read; // mm_interconnect_0:slave_0_avalon_slave_0_read -> slave_0:avs_read wire mm_interconnect_0_slave_0_avalon_slave_0_readdatavalid; // slave_0:avs_readdatavalid -> mm_interconnect_0:slave_0_avalon_slave_0_readdatavalid wire mm_interconnect_0_slave_0_avalon_slave_0_write; // mm_interconnect_0:slave_0_avalon_slave_0_write -> slave_0:avs_write wire [7:0] mm_interconnect_0_slave_0_avalon_slave_0_writedata; // mm_interconnect_0:slave_0_avalon_slave_0_writedata -> slave_0:avs_writedata altera_avalon_mm_master_bfm #( .AV_ADDRESS_W (32), .AV_SYMBOL_W (8), .AV_NUMSYMBOLS (4), .AV_BURSTCOUNT_W (3), .AV_READRESPONSE_W (8), .AV_WRITERESPONSE_W (8), .USE_READ (1), .USE_WRITE (1), .USE_ADDRESS (1), .USE_BYTE_ENABLE (1), .USE_BURSTCOUNT (1), .USE_READ_DATA (1), .USE_READ_DATA_VALID (1), .USE_WRITE_DATA (1), .USE_BEGIN_TRANSFER (0), .USE_BEGIN_BURST_TRANSFER (0), .USE_WAIT_REQUEST (1), .USE_TRANSACTIONID (0), .USE_WRITERESPONSE (0), .USE_READRESPONSE (0), .USE_CLKEN (0), .AV_CONSTANT_BURST_BEHAVIOR (1), .AV_BURST_LINEWRAP (1), .AV_BURST_BNDR_ONLY (1), .AV_MAX_PENDING_READS (0), .AV_MAX_PENDING_WRITES (0), .AV_FIX_READ_LATENCY (1), .AV_READ_WAIT_TIME (1), .AV_WRITE_WAIT_TIME (0), .REGISTER_WAITREQUEST (0), .AV_REGISTERINCOMINGSIGNALS (0), .VHDL_ID (0) ) master_0 ( .clk (clk_clk), // clk.clk .reset (~reset_reset_n), // clk_reset.reset .avm_address (master_0_m0_address), // m0.address .avm_burstcount (master_0_m0_burstcount), // .burstcount .avm_readdata (master_0_m0_readdata), // .readdata .avm_writedata (master_0_m0_writedata), // .writedata .avm_waitrequest (master_0_m0_waitrequest), // .waitrequest .avm_write (master_0_m0_write), // .write .avm_read (master_0_m0_read), // .read .avm_byteenable (master_0_m0_byteenable), // .byteenable .avm_readdatavalid (master_0_m0_readdatavalid), // .readdatavalid .avm_begintransfer (), // (terminated) .avm_beginbursttransfer (), // (terminated) .avm_arbiterlock (), // (terminated) .avm_lock (), // (terminated) .avm_debugaccess (), // (terminated) .avm_transactionid (), // (terminated) .avm_readid (8'b00000000), // (terminated) .avm_writeid (8'b00000000), // (terminated) .avm_clken (), // (terminated) .avm_response (2'b00), // (terminated) .avm_writeresponsevalid (1'b0), // (terminated) .avm_readresponse (8'b00000000), // (terminated) .avm_writeresponse (8'b00000000) // (terminated) ); pulse_sample_qsys #( .seq_sample_count_width (21), .offset_depth (10), .pulse_width_depth (16), .code_depth (128), .code_depth_2n (7), .shunt_duration (111), .shunt_depth (7) ) slave_0 ( .avs_address (mm_interconnect_0_slave_0_avalon_slave_0_address), // avalon_slave_0.address .avs_read (mm_interconnect_0_slave_0_avalon_slave_0_read), // .read .avs_readdata (mm_interconnect_0_slave_0_avalon_slave_0_readdata), // .readdata .avs_write (mm_interconnect_0_slave_0_avalon_slave_0_write), // .write .avs_writedata (mm_interconnect_0_slave_0_avalon_slave_0_writedata), // .writedata .avs_waitrequest (mm_interconnect_0_slave_0_avalon_slave_0_waitrequest), // .waitrequest .avs_readdatavalid (mm_interconnect_0_slave_0_avalon_slave_0_readdatavalid), // .readdatavalid .reset (~reset_reset_n), // reset.reset .clk_sys (clk_clk), // clk_sys.clk .laser_current (laser_laser_current), // laser.laser_current .laser_pulse (laser_laser_pulse), // .laser_pulse .laser_shunt (laser_laser_shunt) // .laser_shunt ); avlm_avls_1x1_mm_interconnect_0 mm_interconnect_0 ( .clk_clk_clk (clk_clk), // clk_clk.clk .master_0_clk_reset_reset_bridge_in_reset_reset (~reset_reset_n), // master_0_clk_reset_reset_bridge_in_reset.reset .master_0_m0_address (master_0_m0_address), // master_0_m0.address .master_0_m0_waitrequest (master_0_m0_waitrequest), // .waitrequest .master_0_m0_burstcount (master_0_m0_burstcount), // .burstcount .master_0_m0_byteenable (master_0_m0_byteenable), // .byteenable .master_0_m0_read (master_0_m0_read), // .read .master_0_m0_readdata (master_0_m0_readdata), // .readdata .master_0_m0_readdatavalid (master_0_m0_readdatavalid), // .readdatavalid .master_0_m0_write (master_0_m0_write), // .write .master_0_m0_writedata (master_0_m0_writedata), // .writedata .slave_0_avalon_slave_0_address (mm_interconnect_0_slave_0_avalon_slave_0_address), // slave_0_avalon_slave_0.address .slave_0_avalon_slave_0_write (mm_interconnect_0_slave_0_avalon_slave_0_write), // .write .slave_0_avalon_slave_0_read (mm_interconnect_0_slave_0_avalon_slave_0_read), // .read .slave_0_avalon_slave_0_readdata (mm_interconnect_0_slave_0_avalon_slave_0_readdata), // .readdata .slave_0_avalon_slave_0_writedata (mm_interconnect_0_slave_0_avalon_slave_0_writedata), // .writedata .slave_0_avalon_slave_0_readdatavalid (mm_interconnect_0_slave_0_avalon_slave_0_readdatavalid), // .readdatavalid .slave_0_avalon_slave_0_waitrequest (mm_interconnect_0_slave_0_avalon_slave_0_waitrequest) // .waitrequest ); endmodule