execve("/opt/intelFPGA/23.1/quartus/bin/quartus", ["/opt/intelFPGA/23.1/quartus/bin/"..., "--64bit"], 0x7ffeb1ba0278 /* 63 vars */) = 0 brk(NULL) = 0x5e314135c000 access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=131979, ...}) = 0 mmap(NULL, 131979, PROT_READ, MAP_PRIVATE, 3, 0) = 0x79a891fa0000 close(3) = 0 openat(AT_FDCWD, "/usr/lib/libreadline.so.8", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=343064, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x79a891f9e000 mmap(NULL, 350904, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x79a891f48000 mmap(0x79a891f5d000, 188416, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x15000) = 0x79a891f5d000 mmap(0x79a891f8b000, 36864, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x43000) = 0x79a891f8b000 mmap(0x79a891f94000, 36864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4b000) = 0x79a891f94000 mmap(0x79a891f9d000, 2744, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x79a891f9d000 close(3) = 0 openat(AT_FDCWD, "/usr/lib/libc.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\340_\2\0\0\0\0\0"..., 832) = 832 pread64(3, "\6\0\0\0\4\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0"..., 784, 64) = 784 fstat(3, {st_mode=S_IFREG|0755, st_size=2014520, ...}) = 0 pread64(3, "\6\0\0\0\4\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0"..., 784, 64) = 784 mmap(NULL, 2034616, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x79a891d57000 mmap(0x79a891d7b000, 1511424, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x24000) = 0x79a891d7b000 mmap(0x79a891eec000, 319488, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x195000) = 0x79a891eec000 mmap(0x79a891f3a000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1e3000) = 0x79a891f3a000 mmap(0x79a891f40000, 31672, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x79a891f40000 close(3) = 0 openat(AT_FDCWD, "/usr/lib/libncursesw.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=453896, ...}) = 0 mmap(NULL, 453856, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x79a891ce8000 mmap(0x79a891cf5000, 290816, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd000) = 0x79a891cf5000 mmap(0x79a891d3c000, 90112, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x54000) = 0x79a891d3c000 mmap(0x79a891d52000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6a000) = 0x79a891d52000 close(3) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x79a891ce6000 arch_prctl(ARCH_SET_FS, 0x79a891ce6b80) = 0 set_tid_address(0x79a891ce6e50) = 375096 set_robust_list(0x79a891ce6e60, 24) = 0 rseq(0x79a891ce74a0, 0x20, 0, 0x53053053) = 0 mprotect(0x79a891f3a000, 16384, PROT_READ) = 0 mprotect(0x79a891d52000, 16384, PROT_READ) = 0 mprotect(0x79a891f94000, 12288, PROT_READ) = 0 mprotect(0x5e31092c7000, 12288, PROT_READ) = 0 mprotect(0x79a891ffb000, 8192, PROT_READ) = 0 prlimit64(0, RLIMIT_STACK, NULL, {rlim_cur=8192*1024, rlim_max=RLIM64_INFINITY}) = 0 munmap(0x79a891fa0000, 131979) = 0 openat(AT_FDCWD, "/dev/tty", O_RDWR|O_NONBLOCK) = 3 close(3) = 0 getrandom("\xfe\x81\xdb\x89\x67\xfb\xf2\x35", 8, GRND_NONBLOCK) = 8 brk(NULL) = 0x5e314135c000 brk(0x5e314137d000) = 0x5e314137d000 openat(AT_FDCWD, "/usr/lib/locale/locale-archive", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=3060144, ...}) = 0 mmap(NULL, 3060144, PROT_READ, MAP_PRIVATE, 3, 0) = 0x79a891800000 close(3) = 0 openat(AT_FDCWD, "/usr/lib/gconv/gconv-modules.cache", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/gconv/gconv-modules", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=3916, ...}) = 0 read(3, "# GNU libc iconv configuration.\n"..., 4096) = 3916 read(3, "", 4096) = 0 close(3) = 0 openat(AT_FDCWD, "/usr/lib/gconv/gconv-modules.d", O_RDONLY|O_NONBLOCK|O_CLOEXEC|O_DIRECTORY) = 3 fstat(3, {st_mode=S_IFDIR|0755, st_size=4096, ...}) = 0 getdents64(3, 0x5e314135ff20 /* 3 entries */, 32768) = 96 openat(AT_FDCWD, "/usr/lib/gconv/gconv-modules.d/gconv-modules-extra.conf", O_RDONLY|O_CLOEXEC) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=53974, ...}) = 0 read(4, "# GNU libc iconv configuration.\n"..., 4096) = 4096 read(4, "B1002//\tJUS_I.B1.002//\nmodule\tJU"..., 4096) = 4096 read(4, "59-5//\nalias\tISO_8859-5//\t\tISO-8"..., 4096) = 4096 read(4, "59-16//\t\tINTERNAL\t\tISO8859-16\t1\n"..., 4096) = 4096 read(4, "-SE-A\t1\nmodule\tINTERNAL\t\tEBCDIC-"..., 4096) = 4096 read(4, "97\t\t1\n\n#\tfrom\t\t\tto\t\t\tmodule\t\tcos"..., 4096) = 4096 read(4, "1\n\n#\tfrom\t\t\tto\t\t\tmodule\t\tcost\nal"..., 4096) = 4096 read(4, "6//\t\tIBM1046//\nalias\tCP1046//\t\tI"..., 4096) = 4096 read(4, "\tto\t\t\tmodule\t\tcost\nalias\tRUSCII/"..., 4096) = 4096 brk(0x5e314139e000) = 0x5e314139e000 read(4, "03//\nmodule\tCSN_369103//\t\tINTERN"..., 4096) = 4096 read(4, "\tmodule\t\tcost\nalias\tISO-IR-8-1//"..., 4096) = 4096 read(4, "IBM1156\t\t1\n\n#\tfrom\t\t\tto\t\t\tmodule"..., 4096) = 4096 read(4, "\t\tIBM1166//\nalias\tCP1166//\t\tIBM1"..., 4096) = 4096 read(4, "alias\tROMAN9//\t\tHP-ROMAN9//\nalia"..., 4096) = 726 read(4, "", 4096) = 0 close(4) = 0 getdents64(3, 0x5e314135ff20 /* 0 entries */, 32768) = 0 close(3) = 0 futex(0x79a891f3f72c, FUTEX_WAKE_PRIVATE, 2147483647) = 0 getuid() = 1000 getgid() = 1000 geteuid() = 1000 getegid() = 1000 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=0}, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGQUIT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=0}, 8) = 0 rt_sigaction(SIGQUIT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGTSTP, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=0}, 8) = 0 rt_sigaction(SIGTSTP, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGTTIN, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=0}, 8) = 0 rt_sigaction(SIGTTIN, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGTTOU, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=0}, 8) = 0 rt_sigaction(SIGTTOU, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigaction(SIGQUIT, {sa_handler=SIG_IGN, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 uname({sysname="Linux", nodename="nirvaware", ...}) = 0 newfstatat(AT_FDCWD, "/home/nirva", {st_mode=S_IFDIR|0700, st_size=4096, ...}, 0) = 0 newfstatat(AT_FDCWD, ".", {st_mode=S_IFDIR|0700, st_size=4096, ...}, 0) = 0 newfstatat(AT_FDCWD, "/home", {st_mode=S_IFDIR|0755, st_size=4096, ...}, 0) = 0 newfstatat(AT_FDCWD, "/home/nirva", {st_mode=S_IFDIR|0700, st_size=4096, ...}, 0) = 0 getpid() = 375096 getppid() = 375093 getpid() = 375096 getppid() = 375093 getpid() = 375096 getppid() = 375093 getpgrp() = 375093 ioctl(2, TIOCGPGRP, [375093]) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 prlimit64(0, RLIMIT_NPROC, NULL, {rlim_cur=62405, rlim_max=62405}) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/bin/quartus", O_RDONLY) = 3 newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/bin/quartus", {st_mode=S_IFREG|0555, st_size=2189, ...}, 0) = 0 ioctl(3, TCGETS, 0x7ffebd933140) = -1 ENOTTY (Inappropriate ioctl for device) lseek(3, 0, SEEK_CUR) = 0 read(3, "#!/bin/bash\n\n# Copyright (c) 202"..., 80) = 80 lseek(3, 0, SEEK_SET) = 0 prlimit64(0, RLIMIT_NOFILE, NULL, {rlim_cur=1024, rlim_max=512*1024}) = 0 fcntl(255, F_GETFD) = -1 EBADF (Bad file descriptor) dup2(3, 255) = 255 close(3) = 0 fcntl(255, F_SETFD, FD_CLOEXEC) = 0 fcntl(255, F_GETFL) = 0x8000 (flags O_RDONLY|O_LARGEFILE) fstat(255, {st_mode=S_IFREG|0555, st_size=2189, ...}) = 0 lseek(255, 0, SEEK_CUR) = 0 read(255, "#!/bin/bash\n\n# Copyright (c) 202"..., 2189) = 2189 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 lseek(255, -463, SEEK_CUR) = 1726 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375097 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "/opt/intelFPGA/23.1/quartus/bin\n", 4096) = 32 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375097, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375097 wait4(-1, 0x7ffebd930790, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 32 read(3, "", 4096) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375098 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "/opt/intelFPGA/23.1/quartus\n", 4096) = 28 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375098, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375098 wait4(-1, 0x7ffebd9307d0, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 28 read(3, "", 4096) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 read(255, "\nif test `case \"$QUARTUS_ROOTDIR"..., 2189) = 463 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 lseek(255, -307, SEEK_CUR) = 1882 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375099 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "match\n", 4096) = 6 read(3, "", 4096) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375099, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375099 wait4(-1, 0x7ffebd930b50, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 read(255, "\nexport CMD_NAME=`basename $0`\n\n"..., 2189) = 307 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 lseek(255, -276, SEEK_CUR) = 1913 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375100 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "quartus\n", 4096) = 8 read(3, "", 4096) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375100, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375100 wait4(-1, 0x7ffebd930c90, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 read(255, "\n# Need this so shell won't try "..., 2189) = 276 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/adm/qenv.sh", O_RDONLY) = 3 fstat(3, {st_mode=S_IFREG|0555, st_size=4436, ...}) = 0 read(3, "#!/bin/bash\n# Copyright (c) 2012"..., 4436) = 4436 close(3) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 fcntl(0, F_GETFD) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [CHLD], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [CHLD], 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [INT TERM CHLD], 8) = 0 rt_sigprocmask(SIG_SETMASK, [INT TERM CHLD], NULL, 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375101 rt_sigprocmask(SIG_SETMASK, [CHLD], NULL, 8) = 0 close(4) = 0 close(4) = -1 EBADF (Bad file descriptor) rt_sigprocmask(SIG_BLOCK, NULL, [CHLD], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [CHLD], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375102 rt_sigprocmask(SIG_SETMASK, [CHLD], NULL, 8) = 0 close(3) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [CHLD], 8) = 0 rt_sigprocmask(SIG_SETMASK, [CHLD], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [CHLD], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], 0, NULL) = 375101 wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 1}], 0, NULL) = 375102 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 ioctl(2, TIOCGWINSZ, {ws_row=43, ws_col=188, ws_xpixel=1507, ws_ypixel=746}) = 0 rt_sigprocmask(SIG_SETMASK, [CHLD], NULL, 8) = 0 close(3) = -1 EBADF (Bad file descriptor) rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375101, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, 0x7ffebd930d10, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[]}) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375103 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "Linux\n", 4096) = 6 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375103, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375103 wait4(-1, 0x7ffebd92fc90, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 6 read(3, "", 4096) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375104 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "6.12.10-arch1-1\n", 4096) = 16 read(3, "", 4096) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375104, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375104 wait4(-1, 0x7ffebd92fdd0, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 brk(0x5e31413bf000) = 0x5e31413bf000 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375105 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "#1 SMP PREEMPT_DYNAMIC Sat, 18 J"..., 4096) = 55 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375105, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375105 wait4(-1, 0x7ffebd92fd90, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 55 read(3, "", 4096) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375106 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "", 4096) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375106, si_uid=1000, si_status=1, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 1}], WNOHANG, NULL) = 375106 wait4(-1, 0x7ffebd92fb50, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375109 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "x86_64\n", 4096) = 7 read(3, "", 4096) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375109, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375109 wait4(-1, 0x7ffebd9303d0, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 pipe2([3, 4], 0) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375110 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 close(4) = 0 rt_sigprocmask(SIG_BLOCK, [INT], [], 8) = 0 read(3, "11th Gen Intel(R) Core(TM) i7-11"..., 4096) = 47 read(3, "", 4096) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375110, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], WNOHANG, NULL) = 375110 wait4(-1, 0x7ffebd9303d0, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[INT]}) = 0 close(3) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 newfstatat(AT_FDCWD, ".", {st_mode=S_IFDIR|0700, st_size=4096, ...}, 0) = 0 newfstatat(AT_FDCWD, "/usr/local/sbin/grep", 0x7ffebd9323e0, 0) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/usr/local/bin/grep", 0x7ffebd9323e0, 0) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/usr/bin/grep", {st_mode=S_IFREG|0755, st_size=153840, ...}, 0) = 0 newfstatat(AT_FDCWD, "/usr/bin/grep", {st_mode=S_IFREG|0755, st_size=153840, ...}, 0) = 0 geteuid() = 1000 getegid() = 1000 getuid() = 1000 getgid() = 1000 access("/usr/bin/grep", X_OK) = 0 newfstatat(AT_FDCWD, "/usr/bin/grep", {st_mode=S_IFREG|0755, st_size=153840, ...}, 0) = 0 geteuid() = 1000 getegid() = 1000 getuid() = 1000 getgid() = 1000 access("/usr/bin/grep", R_OK) = 0 rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [INT TERM CHLD], [], 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [INT TERM CHLD], 8) = 0 rt_sigprocmask(SIG_SETMASK, [INT TERM CHLD], NULL, 8) = 0 clone(child_stack=NULL, flags=CLONE_CHILD_CLEARTID|CLONE_CHILD_SETTID|SIGCHLD, child_tidptr=0x79a891ce6e50) = 375114 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 rt_sigprocmask(SIG_BLOCK, [CHLD], [], 8) = 0 rt_sigaction(SIGINT, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 wait4(-1, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], 0, NULL) = 375114 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e31092101e0, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 ioctl(2, TIOCGWINSZ, {ws_row=43, ws_col=188, ws_xpixel=1507, ws_ypixel=746}) = 0 rt_sigprocmask(SIG_SETMASK, [], NULL, 8) = 0 --- SIGCHLD {si_signo=SIGCHLD, si_code=CLD_EXITED, si_pid=375114, si_uid=1000, si_status=0, si_utime=0, si_stime=0} --- wait4(-1, 0x7ffebd931850, WNOHANG, NULL) = -1 ECHILD (No child processes) rt_sigreturn({mask=[]}) = 0 newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64", {st_mode=S_IFDIR|0755, st_size=69632, ...}, 0) = 0 newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/adm/qtb.sh", 0x7ffebd9324b0, 0) = -1 ENOENT (No such file or directory) rt_sigprocmask(SIG_BLOCK, NULL, [], 8) = 0 newfstatat(AT_FDCWD, ".", {st_mode=S_IFDIR|0700, st_size=4096, ...}, 0) = 0 newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/adm/quartus", 0x7ffebd932620, 0) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/quartus", {st_mode=S_IFREG|0755, st_size=25704, ...}, 0) = 0 newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/quartus", {st_mode=S_IFREG|0755, st_size=25704, ...}, 0) = 0 geteuid() = 1000 getegid() = 1000 getuid() = 1000 getgid() = 1000 access("/opt/intelFPGA/23.1/quartus/linux64/quartus", X_OK) = 0 newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/quartus", {st_mode=S_IFREG|0755, st_size=25704, ...}, 0) = 0 geteuid() = 1000 getegid() = 1000 getuid() = 1000 getgid() = 1000 access("/opt/intelFPGA/23.1/quartus/linux64/quartus", R_OK) = 0 rt_sigaction(SIGINT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGQUIT, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, {sa_handler=SIG_IGN, sa_mask=[], sa_flags=SA_RESTORER, sa_restorer=0x79a891d941d0}, 8) = 0 rt_sigaction(SIGCHLD, {sa_handler=SIG_DFL, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, {sa_handler=0x5e310920da60, sa_mask=[], sa_flags=SA_RESTORER|SA_RESTART, sa_restorer=0x79a891d941d0}, 8) = 0 execve("/opt/intelFPGA/23.1/quartus/linux64/quartus", ["quartus", "--64bit"], 0x5e3141395730 /* 81 vars */) = 0 brk(NULL) = 0x5abcfe7c3000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a837000 access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/glibc-hwcaps/x86-64-v4/libsys_ictq.so", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/glibc-hwcaps/x86-64-v4/", 0x7ffec5848a90, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/glibc-hwcaps/x86-64-v3/libsys_ictq.so", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/glibc-hwcaps/x86-64-v3/", 0x7ffec5848a90, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/glibc-hwcaps/x86-64-v2/libsys_ictq.so", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/glibc-hwcaps/x86-64-v2/", 0x7ffec5848a90, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_ictq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=50384, ...}) = 0 mmap(NULL, 41760, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a82c000 mmap(0x7b3a0a835000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8000) = 0x7b3a0a835000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_qgq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=234792, ...}) = 0 mmap(NULL, 180384, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a7ff000 mmap(0x7b3a0a828000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x28000) = 0x7b3a0a828000 mmap(0x7b3a0a82b000, 160, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a82b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_qsysipc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=272216, ...}) = 0 mmap(NULL, 198400, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a7ce000 mmap(0x7b3a0a7fb000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2c000) = 0x7b3a0a7fb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_qui.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2282760, ...}) = 0 mmap(NULL, 1824680, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a610000 mprotect(0x7b3a0a7b3000, 4096, PROT_NONE) = 0 mmap(0x7b3a0a7b4000, 86016, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a3000) = 0x7b3a0a7b4000 mmap(0x7b3a0a7c9000, 18344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a7c9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_pjc_tcl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=364256, ...}) = 0 mmap(NULL, 318336, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a5c2000 mmap(0x7b3a0a60b000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x48000) = 0x7b3a0a60b000 mmap(0x7b3a0a60f000, 2944, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a60f000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libprj_asl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=264864, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a5c0000 mmap(NULL, 204680, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a58e000 mprotect(0x7b3a0a5bd000, 4096, PROT_NONE) = 0 mmap(0x7b3a0a5be000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2f000) = 0x7b3a0a5be000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_fin.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=290424, ...}) = 0 mmap(NULL, 218640, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a558000 mprotect(0x7b3a0a589000, 4096, PROT_NONE) = 0 mmap(0x7b3a0a58a000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x31000) = 0x7b3a0a58a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libace_adb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=5938424, ...}) = 0 mmap(NULL, 4706896, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a000000 mmap(0x7b3a0a458000, 106496, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x457000) = 0x7b3a0a458000 mmap(0x7b3a0a472000, 45648, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a472000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_rpt.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2639600, ...}) = 0 mmap(NULL, 2279120, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09c00000 mprotect(0x7b3a09e23000, 4096, PROT_NONE) = 0 mmap(0x7b3a09e24000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x223000) = 0x7b3a09e24000 mmap(0x7b3a09e2c000, 1744, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a09e2c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/liblegality_lregion.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=262096, ...}) = 0 mmap(NULL, 223120, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a521000 mmap(0x7b3a0a556000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x34000) = 0x7b3a0a556000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libace_acest.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=163800, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a51f000 mmap(NULL, 142792, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a4fc000 mmap(0x7b3a0a51b000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1e000) = 0x7b3a0a51b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libprj_asl_dc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=164704, ...}) = 0 mmap(NULL, 129120, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a4dc000 mprotect(0x7b3a0a4f9000, 4096, PROT_NONE) = 0 mmap(0x7b3a0a4fa000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d000) = 0x7b3a0a4fa000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_flow.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=617184, ...}) = 0 mmap(NULL, 478608, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09f8b000 mprotect(0x7b3a09ffa000, 4096, PROT_NONE) = 0 mmap(0x7b3a09ffb000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6f000) = 0x7b3a09ffb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_hcu.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=41776, ...}) = 0 mmap(NULL, 33568, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a4d3000 mmap(0x7b3a0a4da000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b3a0a4da000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_rcomp.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=210992, ...}) = 0 mmap(NULL, 165464, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a4aa000 mprotect(0x7b3a0a4d0000, 4096, PROT_NONE) = 0 mmap(0x7b3a0a4d1000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x26000) = 0x7b3a0a4d1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_py.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=50328, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a4a8000 mmap(NULL, 38072, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a49e000 mmap(0x7b3a0a4a6000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b3a0a4a6000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_ice.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=458424, ...}) = 0 mmap(NULL, 340976, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09f37000 mprotect(0x7b3a09f86000, 4096, PROT_NONE) = 0 mmap(0x7b3a09f87000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4f000) = 0x7b3a09f87000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_sli.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=308352, ...}) = 0 mmap(NULL, 210376, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09f03000 mmap(0x7b3a09f32000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2e000) = 0x7b3a09f32000 mmap(0x7b3a09f36000, 1480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a09f36000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_chi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=239536, ...}) = 0 mmap(NULL, 190968, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09ed4000 mprotect(0x7b3a09f00000, 4096, PROT_NONE) = 0 mmap(0x7b3a09f01000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2c000) = 0x7b3a09f01000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_hapi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=46208, ...}) = 0 mmap(NULL, 53656, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a490000 mmap(0x7b3a0a498000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b3a0a498000 mmap(0x7b3a0a49a000, 12696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a49a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libjtag_client.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1994320, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a48e000 mmap(NULL, 420768, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09e6d000 mprotect(0x7b3a09ed0000, 4096, PROT_NONE) = 0 mmap(0x7b3a09ed1000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x63000) = 0x7b3a09ed1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_atcio.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=116224, ...}) = 0 mmap(NULL, 88144, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09e57000 mmap(0x7b3a09e6b000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x13000) = 0x7b3a09e6b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_sdr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2264432, ...}) = 0 mmap(NULL, 1859008, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09a3a000 mprotect(0x7b3a09bf3000, 4096, PROT_NONE) = 0 mmap(0x7b3a09bf4000, 45056, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1b9000) = 0x7b3a09bf4000 mmap(0x7b3a09bff000, 3520, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a09bff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsaui_eui.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=95712, ...}) = 0 mmap(NULL, 82928, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09e42000 mprotect(0x7b3a09e54000, 4096, PROT_NONE) = 0 mmap(0x7b3a09e55000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12000) = 0x7b3a09e55000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_wizmancmd_sh.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1175032, ...}) = 0 mmap(NULL, 1050392, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09939000 mprotect(0x7b3a09a34000, 4096, PROT_NONE) = 0 mmap(0x7b3a09a35000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xfb000) = 0x7b3a09a35000 mmap(0x7b3a09a39000, 1816, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a09a39000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_rules_validator.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=322760, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a48c000 mmap(NULL, 288961, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a098f2000 mmap(0x7b3a09936000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x43000) = 0x7b3a09936000 mmap(0x7b3a09938000, 2241, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a09938000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmlib_int.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=71024, ...}) = 0 mmap(NULL, 64688, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09e32000 mmap(0x7b3a09e40000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd000) = 0x7b3a09e40000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_regexp.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=110512, ...}) = 0 mmap(NULL, 86723, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a098dc000 mmap(0x7b3a098f0000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x13000) = 0x7b3a098f0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_info.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=202280, ...}) = 0 mmap(NULL, 185426, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a098ae000 mprotect(0x7b3a098d9000, 4096, PROT_NONE) = 0 mmap(0x7b3a098da000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2b000) = 0x7b3a098da000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_xml_parser.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=59560, ...}) = 0 mmap(NULL, 53825, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0a47e000 mmap(0x7b3a0a489000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa000) = 0x7b3a0a489000 mmap(0x7b3a0a48b000, 577, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0a48b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libedt_gio.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1011632, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a09e30000 mmap(NULL, 866641, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a097da000 mprotect(0x7b3a09896000, 4096, PROT_NONE) = 0 mmap(0x7b3a09897000, 94208, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xbc000) = 0x7b3a09897000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsynth_sio.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=67368, ...}) = 0 mmap(NULL, 58200, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a097cb000 mmap(0x7b3a097d8000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b3a097d8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgcl_gtoq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=245864, ...}) = 0 mmap(NULL, 204008, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09799000 mprotect(0x7b3a097c7000, 4096, PROT_NONE) = 0 mmap(0x7b3a097c8000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2e000) = 0x7b3a097c8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgcl_cglq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=55560, ...}) = 0 mmap(NULL, 41744, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0978e000 mmap(0x7b3a09797000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8000) = 0x7b3a09797000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgcl_afcq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=7386208, ...}) = 0 mmap(NULL, 6994760, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09000000 mprotect(0x7b3a09689000, 4096, PROT_NONE) = 0 mmap(0x7b3a0968a000, 139264, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x689000) = 0x7b3a0968a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgcl_afcq_tb2.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=21344, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a09e2e000 mmap(NULL, 16832, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09789000 mmap(0x7b3a0978c000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b3a0978c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgcl_cfgq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=158848, ...}) = 0 mmap(NULL, 124072, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0976a000 mprotect(0x7b3a09785000, 4096, PROT_NONE) = 0 mmap(0x7b3a09786000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1b000) = 0x7b3a09786000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_tinyxml2.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=105208, ...}) = 0 mmap(NULL, 83473, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a09755000 mprotect(0x7b3a09767000, 4096, PROT_NONE) = 0 mmap(0x7b3a09768000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12000) = 0x7b3a09768000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Svg.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0P\254\1\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=470272, ...}) = 0 mmap(NULL, 372856, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a096f9000 mprotect(0x7b3a09712000, 258048, PROT_NONE) = 0 mmap(0x7b3a09712000, 208896, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x19000) = 0x7b3a09712000 mmap(0x7b3a09745000, 45056, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4c000) = 0x7b3a09745000 mmap(0x7b3a09751000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x57000) = 0x7b3a09751000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_qtk.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1886792, ...}) = 0 mmap(NULL, 1594120, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08e7a000 mmap(0x7b3a08ff5000, 40960, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x17a000) = 0x7b3a08ff5000 mmap(0x7b3a08fff000, 776, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a08fff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsynth_sgn_qic_dpi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=208016, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096f7000 mmap(NULL, 150672, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a096d2000 mprotect(0x7b3a096f3000, 4096, PROT_NONE) = 0 mmap(0x7b3a096f4000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x21000) = 0x7b3a096f4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_sci.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=870752, ...}) = 0 mmap(NULL, 644144, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08ddc000 mmap(0x7b3a08e72000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x95000) = 0x7b3a08e72000 mmap(0x7b3a08e78000, 5168, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a08e78000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsld_sad.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=451872, ...}) = 0 mmap(NULL, 357808, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08d84000 mprotect(0x7b3a08dd7000, 4096, PROT_NONE) = 0 mmap(0x7b3a08dd8000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x53000) = 0x7b3a08dd8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_ipqx.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=364112, ...}) = 0 mmap(NULL, 302064, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08d3a000 mprotect(0x7b3a08d80000, 4096, PROT_NONE) = 0 mmap(0x7b3a08d81000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x46000) = 0x7b3a08d81000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtpi_miu.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=57960, ...}) = 0 mmap(NULL, 46072, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a096c6000 mmap(0x7b3a096d0000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9000) = 0x7b3a096d0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_llu.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=995944, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096c4000 mmap(NULL, 841432, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08c6c000 mprotect(0x7b3a08d33000, 4096, PROT_NONE) = 0 mmap(0x7b3a08d34000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc7000) = 0x7b3a08d34000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_tdc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=917088, ...}) = 0 mmap(NULL, 824256, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08ba2000 mprotect(0x7b3a08c53000, 4096, PROT_NONE) = 0 mmap(0x7b3a08c54000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xb1000) = 0x7b3a08c54000 mmap(0x7b3a08c58000, 78784, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a08c58000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_sta.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=10124672, ...}) = 0 mmap(NULL, 8008080, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08200000 mprotect(0x7b3a08977000, 4096, PROT_NONE) = 0 mmap(0x7b3a08978000, 155648, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x777000) = 0x7b3a08978000 mmap(0x7b3a0899e000, 20880, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0899e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_ddrtcl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=523536, ...}) = 0 mmap(NULL, 439880, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08b36000 mmap(0x7b3a08b9e000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x67000) = 0x7b3a08b9e000 mmap(0x7b3a08ba1000, 1608, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a08ba1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_a2t.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1706640, ...}) = 0 mmap(NULL, 1417232, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a089db000 mmap(0x7b3a08b29000, 49152, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14d000) = 0x7b3a08b29000 mmap(0x7b3a08b35000, 16, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a08b35000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dygr_fdi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1018608, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096c2000 mmap(NULL, 794928, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0813d000 mmap(0x7b3a081f9000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xbb000) = 0x7b3a081f9000 mmap(0x7b3a081fe000, 4400, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a081fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_tapi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=314064, ...}) = 0 mmap(NULL, 247296, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a08100000 mmap(0x7b3a0813a000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x39000) = 0x7b3a0813a000 mmap(0x7b3a0813c000, 1536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0813c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_tis.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4265808, ...}) = 0 mmap(NULL, 3430720, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07c00000 mprotect(0x7b3a07f14000, 4096, PROT_NONE) = 0 mmap(0x7b3a07f15000, 114688, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x314000) = 0x7b3a07f15000 mmap(0x7b3a07f31000, 84288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a07f31000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_b2t.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=10485000, ...}) = 0 mmap(NULL, 10335504, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07200000 mprotect(0x7b3a0790f000, 4096, PROT_NONE) = 0 mmap(0x7b3a07910000, 2895872, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x70f000) = 0x7b3a07910000 mmap(0x7b3a07bd3000, 34064, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a07bd3000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dlib.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2318936, ...}) = 0 mmap(NULL, 1814056, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07045000 mmap(0x7b3a071ed000, 49152, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a7000) = 0x7b3a071ed000 mmap(0x7b3a071f9000, 28200, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a071f9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_tim_rc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=334936, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096c0000 mmap(NULL, 306760, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a080b5000 mprotect(0x7b3a080f2000, 4096, PROT_NONE) = 0 mmap(0x7b3a080f3000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3d000) = 0x7b3a080f3000 mmap(0x7b3a080f5000, 44616, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a080f5000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_pti.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=3255224, ...}) = 0 mmap(NULL, 2651728, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06c00000 mprotect(0x7b3a06e72000, 4096, PROT_NONE) = 0 mmap(0x7b3a06e73000, 40960, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x272000) = 0x7b3a06e73000 mmap(0x7b3a06e7d000, 42576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a06e7d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_fdi_data.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1551912, ...}) = 0 mmap(NULL, 1085096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07fac000 mmap(0x7b3a080aa000, 36864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xfd000) = 0x7b3a080aa000 mmap(0x7b3a080b3000, 7848, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a080b3000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_dist.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=133800, ...}) = 0 mmap(NULL, 96504, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a089c3000 mprotect(0x7b3a089d8000, 4096, PROT_NONE) = 0 mmap(0x7b3a089d9000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x15000) = 0x7b3a089d9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_ipsta.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=299592, ...}) = 0 mmap(NULL, 227528, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07f74000 mmap(0x7b3a07fa9000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x34000) = 0x7b3a07fa9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dspf.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=987960, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096be000 mmap(NULL, 844880, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06f76000 mmap(0x7b3a07041000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xca000) = 0x7b3a07041000 mmap(0x7b3a07044000, 1104, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a07044000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libqcl_clk.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1231152, ...}) = 0 mmap(NULL, 911112, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06e97000 mprotect(0x7b3a06f6d000, 4096, PROT_NONE) = 0 mmap(0x7b3a06f6e000, 28672, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd6000) = 0x7b3a06f6e000 mmap(0x7b3a06f75000, 1800, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a06f75000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dcalc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=11934280, ...}) = 0 mmap(NULL, 9987744, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06200000 mprotect(0x7b3a06ad8000, 4096, PROT_NONE) = 0 mmap(0x7b3a06ad9000, 688128, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8d8000) = 0x7b3a06ad9000 mmap(0x7b3a06b81000, 22176, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a06b81000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_qspc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1226544, ...}) = 0 mmap(NULL, 1102088, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a060f2000 mmap(0x7b3a061fa000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x107000) = 0x7b3a061fa000 mmap(0x7b3a061fe000, 4360, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a061fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_rpc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=215024, ...}) = 0 mmap(NULL, 169848, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07f4a000 mprotect(0x7b3a07f71000, 4096, PROT_NONE) = 0 mmap(0x7b3a07f72000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x27000) = 0x7b3a07f72000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_mps.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=167984, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096bc000 mmap(NULL, 127984, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07be0000 mprotect(0x7b3a07bfd000, 4096, PROT_NONE) = 0 mmap(0x7b3a07bfe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d000) = 0x7b3a07bfe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_tim.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1185024, ...}) = 0 mmap(NULL, 1000632, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05ffd000 mprotect(0x7b3a060df000, 4096, PROT_NONE) = 0 mmap(0x7b3a060e0000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe2000) = 0x7b3a060e0000 mmap(0x7b3a060e5000, 50360, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a060e5000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_sin.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2239496, ...}) = 0 mmap(NULL, 1885664, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05e30000 mprotect(0x7b3a05fd8000, 4096, PROT_NONE) = 0 mmap(0x7b3a05fd9000, 139264, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a8000) = 0x7b3a05fd9000 mmap(0x7b3a05ffb000, 5600, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a05ffb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_ioo.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=685248, ...}) = 0 mmap(NULL, 487568, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06b88000 mmap(0x7b3a06bf6000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6d000) = 0x7b3a06bf6000 mmap(0x7b3a06bfe000, 4240, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a06bfe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_nlspc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1631296, ...}) = 0 mmap(NULL, 1395400, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05cdb000 mprotect(0x7b3a05e26000, 4096, PROT_NONE) = 0 mmap(0x7b3a05e27000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14b000) = 0x7b3a05e27000 mmap(0x7b3a05e2c000, 15048, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a05e2c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_superlu.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=145920, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096ba000 mmap(NULL, 124240, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a089a4000 mmap(0x7b3a089c1000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1c000) = 0x7b3a089c1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_blas.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=33184, ...}) = 0 mmap(NULL, 29136, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a096b2000 mmap(0x7b3a096b8000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b3a096b8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_metis.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=415360, ...}) = 0 mmap(NULL, 397465, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05c79000 mmap(0x7b3a05cd9000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5f000) = 0x7b3a05cd9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_core.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=5483440, ...}) = 0 mmap(NULL, 3788136, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05800000 mprotect(0x7b3a05b80000, 4096, PROT_NONE) = 0 mmap(0x7b3a05b81000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x380000) = 0x7b3a05b81000 mmap(0x7b3a05b87000, 89448, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a05b87000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libpgm_options.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=163552, ...}) = 0 mmap(NULL, 129857, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05c59000 mprotect(0x7b3a05c76000, 4096, PROT_NONE) = 0 mmap(0x7b3a05c77000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d000) = 0x7b3a05c77000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libqcl_iopt.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=201256, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096b0000 mmap(NULL, 176984, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05c2d000 mprotect(0x7b3a05c56000, 4096, PROT_NONE) = 0 mmap(0x7b3a05c57000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x29000) = 0x7b3a05c57000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_routing.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=433976, ...}) = 0 mmap(NULL, 338824, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05bda000 mmap(0x7b3a05c2a000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4f000) = 0x7b3a05c2a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_shm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=21288, ...}) = 0 mmap(NULL, 16872, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06e92000 mmap(0x7b3a06e95000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b3a06e95000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_cdb_tcl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2224416, ...}) = 0 mmap(NULL, 762704, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05745000 mmap(0x7b3a057f1000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xab000) = 0x7b3a057f1000 mmap(0x7b3a057f4000, 45904, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a057f4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_qcu.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=778752, ...}) = 0 mmap(NULL, 644160, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a056a7000 mmap(0x7b3a05740000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x98000) = 0x7b3a05740000 mmap(0x7b3a05744000, 1088, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a05744000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtpi_tset.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=32360, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096ae000 mmap(NULL, 25088, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a06e8b000 mmap(0x7b3a06e90000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b3a06e90000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtpi_eti.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=334624, ...}) = 0 mmap(NULL, 276408, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05663000 mmap(0x7b3a0569f000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3b000) = 0x7b3a0569f000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_pjc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1240528, ...}) = 0 mmap(NULL, 930856, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0557f000 mprotect(0x7b3a05653000, 4096, PROT_NONE) = 0 mmap(0x7b3a05654000, 53248, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd4000) = 0x7b3a05654000 mmap(0x7b3a05661000, 5160, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a05661000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_proj.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=171696, ...}) = 0 mmap(NULL, 141984, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05bb7000 mmap(0x7b3a05bd8000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x20000) = 0x7b3a05bd8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_cpt_hdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=41504, ...}) = 0 mmap(NULL, 34088, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05bae000 mmap(0x7b3a05bb5000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b3a05bb5000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtsm_tdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2002200, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a096ac000 mmap(NULL, 1652024, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a053eb000 mmap(0x7b3a05573000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x187000) = 0x7b3a05573000 mmap(0x7b3a0557b000, 13624, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0557b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_vdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1475520, ...}) = 0 mmap(NULL, 1251488, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a052b9000 mprotect(0x7b3a053de000, 4096, PROT_NONE) = 0 mmap(0x7b3a053df000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x125000) = 0x7b3a053df000 mmap(0x7b3a053e4000, 26784, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a053e4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_qhd_dbmui.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=58664, ...}) = 0 mmap(NULL, 46160, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a05ba2000 mprotect(0x7b3a05bab000, 4096, PROT_NONE) = 0 mmap(0x7b3a05bac000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9000) = 0x7b3a05bac000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_qhd.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1104184, ...}) = 0 mmap(NULL, 897000, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a051de000 mmap(0x7b3a052b2000, 28672, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd3000) = 0x7b3a052b2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libperiph_fpp.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2350248, ...}) = 0 mmap(NULL, 1987760, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04ff8000 mmap(0x7b3a051d7000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1de000) = 0x7b3a051d7000 mmap(0x7b3a051dd000, 1200, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a051dd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_rcf.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=785840, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a07f48000 mmap(NULL, 619200, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04f60000 mprotect(0x7b3a04ff2000, 4096, PROT_NONE) = 0 mmap(0x7b3a04ff3000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x92000) = 0x7b3a04ff3000 mmap(0x7b3a04ff6000, 4800, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a04ff6000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_lampas.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=158816, ...}) = 0 mmap(NULL, 128992, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04f40000 mprotect(0x7b3a04f5d000, 4096, PROT_NONE) = 0 mmap(0x7b3a04f5e000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d000) = 0x7b3a04f5e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_ares.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=885920, ...}) = 0 mmap(NULL, 687880, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04e98000 mmap(0x7b3a04f3b000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa2000) = 0x7b3a04f3b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_rapid.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1083440, ...}) = 0 mmap(NULL, 892264, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04dbe000 mmap(0x7b3a04e94000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd5000) = 0x7b3a04e94000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_cdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=6600064, ...}) = 0 mmap(NULL, 4849864, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04800000 mmap(0x7b3a04c7b000, 53248, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x47a000) = 0x7b3a04c7b000 mmap(0x7b3a04c88000, 98504, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a04c88000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_cfg.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=138936, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a07f46000 mmap(NULL, 101248, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04da5000 mmap(0x7b3a04dbc000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x16000) = 0x7b3a04dbc000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_idb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=232096, ...}) = 0 mmap(NULL, 167072, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04d7c000 mmap(0x7b3a04da1000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x24000) = 0x7b3a04da1000 mmap(0x7b3a04da4000, 3232, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a04da4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_qtl_string_match.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14032, ...}) = 0 mmap(NULL, 12440, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a07bdc000 mmap(0x7b3a07bde000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b3a07bde000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_mpp.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=296488, ...}) = 0 mmap(NULL, 234248, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04d42000 mmap(0x7b3a04d79000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x36000) = 0x7b3a04d79000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_logdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=255328, ...}) = 0 mmap(NULL, 249432, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04d05000 mprotect(0x7b3a04d34000, 4096, PROT_NONE) = 0 mmap(0x7b3a04d35000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2f000) = 0x7b3a04d35000 mmap(0x7b3a04d38000, 40536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a04d38000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_rutil.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=144456, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a06e89000 mmap(NULL, 116728, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04ce8000 mmap(0x7b3a04d03000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a000) = 0x7b3a04d03000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libatm_atmx.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=686800, ...}) = 0 mmap(NULL, 547384, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0477a000 mprotect(0x7b3a047fb000, 4096, PROT_NONE) = 0 mmap(0x7b3a047fc000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x81000) = 0x7b3a047fc000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2681368, ...}) = 0 mmap(NULL, 2509816, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04400000 mprotect(0x7b3a04657000, 4096, PROT_NONE) = 0 mmap(0x7b3a04658000, 49152, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x257000) = 0x7b3a04658000 mmap(0x7b3a04664000, 3064, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a04664000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_tinfo.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=8066016, ...}) = 0 mmap(NULL, 8007056, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a03c00000 mmap(0x7b3a042bd000, 937984, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6bc000) = 0x7b3a042bd000 mmap(0x7b3a043a2000, 3472, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a043a2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_b2b.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=337576, ...}) = 0 mmap(NULL, 289081, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04ca1000 mprotect(0x7b3a04cde000, 4096, PROT_NONE) = 0 mmap(0x7b3a04cdf000, 36864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3d000) = 0x7b3a04cdf000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cut.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=15157336, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a05ba0000 mmap(NULL, 12842745, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02e00000 mprotect(0x7b3a039f9000, 4096, PROT_NONE) = 0 mmap(0x7b3a039fa000, 204800, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xbf9000) = 0x7b3a039fa000 mmap(0x7b3a03a2c000, 79609, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a03a2c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_qcu_tb2.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=36280, ...}) = 0 mmap(NULL, 29600, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04772000 mmap(0x7b3a04778000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b3a04778000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsynth_bdd.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=224680, ...}) = 0 mmap(NULL, 195656, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04742000 mmap(0x7b3a04770000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2d000) = 0x7b3a04770000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcbx_util.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=704376, ...}) = 0 mmap(NULL, 681742, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0469b000 mmap(0x7b3a04740000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa4000) = 0x7b3a04740000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_mfam.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=949048, ...}) = 0 mmap(NULL, 752864, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a03b48000 mmap(0x7b3a03bf7000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xae000) = 0x7b3a03bf7000 mmap(0x7b3a03bfc000, 15584, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a03bfc000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libmega_stl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=31320, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a05b9e000 mmap(NULL, 25058, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04694000 mmap(0x7b3a04699000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b3a04699000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libqcl_pll.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=853784, ...}) = 0 mmap(NULL, 740536, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a03a93000 mprotect(0x7b3a03b44000, 4096, PROT_NONE) = 0 mmap(0x7b3a03b45000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xb1000) = 0x7b3a03b45000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_itcl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14632, ...}) = 0 mmap(NULL, 12528, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04690000 mmap(0x7b3a04692000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b3a04692000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_hinf.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=103800, ...}) = 0 mmap(NULL, 66072, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0467f000 mprotect(0x7b3a0468c000, 4096, PROT_NONE) = 0 mmap(0x7b3a0468d000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd000) = 0x7b3a0468d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_rbc_util.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=49520, ...}) = 0 mmap(NULL, 37728, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a04675000 mmap(0x7b3a0467d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b3a0467d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_constra.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1771544, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a04673000 mmap(NULL, 1443304, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02c9f000 mprotect(0x7b3a02df6000, 4096, PROT_NONE) = 0 mmap(0x7b3a02df7000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x157000) = 0x7b3a02df7000 mmap(0x7b3a02dff000, 1512, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a02dff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=18472, ...}) = 0 mmap(NULL, 12441, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0466f000 mmap(0x7b3a04671000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b3a04671000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_emif.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=304096, ...}) = 0 mmap(NULL, 199456, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a043cf000 mmap(0x7b3a043fe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2e000) = 0x7b3a043fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_lvds.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=538984, ...}) = 0 mmap(NULL, 376976, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02c42000 mmap(0x7b3a02c9c000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x59000) = 0x7b3a02c9c000 mmap(0x7b3a02c9e000, 144, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a02c9e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_nf_hssi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=461192, ...}) = 0 mmap(NULL, 331472, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a03a42000 mmap(0x7b3a03a91000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4e000) = 0x7b3a03a91000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_hssi.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=12723656, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0466d000 mmap(NULL, 9407888, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02200000 mmap(0x7b3a02add000, 106496, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8dc000) = 0x7b3a02add000 mmap(0x7b3a02af7000, 7568, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a02af7000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_cv_pll.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1174192, ...}) = 0 mmap(NULL, 856424, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02b70000 mprotect(0x7b3a02c3d000, 4096, PROT_NONE) = 0 mmap(0x7b3a02c3e000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xcd000) = 0x7b3a02c3e000 mmap(0x7b3a02c41000, 360, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a02c41000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_pll.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1251760, ...}) = 0 mmap(NULL, 922304, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0211e000 mmap(0x7b3a021fc000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xdd000) = 0x7b3a021fc000 mmap(0x7b3a021ff000, 704, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a021ff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_generic.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=22915832, ...}) = 0 mmap(NULL, 17172496, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a01000000 mprotect(0x7b3a0202f000, 4096, PROT_NONE) = 0 mmap(0x7b3a02030000, 180224, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x102f000) = 0x7b3a02030000 mmap(0x7b3a0205c000, 18448, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0205c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_util.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=70376, ...}) = 0 mmap(NULL, 41401, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a043c4000 mprotect(0x7b3a043cc000, 4096, PROT_NONE) = 0 mmap(0x7b3a043cd000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8000) = 0x7b3a043cd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_mgr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=415048, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a0466b000 mmap(NULL, 301664, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02b26000 mprotect(0x7b3a02b6b000, 4096, PROT_NONE) = 0 mmap(0x7b3a02b6c000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x45000) = 0x7b3a02b6c000 mmap(0x7b3a02b6f000, 2656, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a02b6f000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_ibr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=412448, ...}) = 0 mmap(NULL, 335440, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a020cc000 mmap(0x7b3a02117000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4a000) = 0x7b3a02117000 mmap(0x7b3a0211d000, 3664, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a0211d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b_bcm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=113016, ...}) = 0 mmap(NULL, 88448, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a043ae000 mmap(0x7b3a043c2000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x13000) = 0x7b3a043c2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b_cfg.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=322504, ...}) = 0 mmap(NULL, 247984, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0208f000 mprotect(0x7b3a020c4000, 4096, PROT_NONE) = 0 mmap(0x7b3a020c5000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x35000) = 0x7b3a020c5000 mmap(0x7b3a020cb000, 2224, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a020cb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_re.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=903776, ...}) = 0 mmap(NULL, 729440, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00f4d000 mmap(0x7b3a00ff5000, 36864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa7000) = 0x7b3a00ff5000 mmap(0x7b3a00ffe000, 4448, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00ffe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_a2c.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=262176, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a04669000 mmap(NULL, 197472, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00f1c000 mmap(0x7b3a00f4a000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2d000) = 0x7b3a00f4a000 mmap(0x7b3a00f4c000, 864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00f4c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_msf.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=193064, ...}) = 0 mmap(NULL, 165936, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02afd000 mprotect(0x7b3a02b23000, 4096, PROT_NONE) = 0 mmap(0x7b3a02b24000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x26000) = 0x7b3a02b24000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cut_dev.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=303216, ...}) = 0 mmap(NULL, 237352, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00ee2000 mprotect(0x7b3a00f19000, 4096, PROT_NONE) = 0 mmap(0x7b3a00f1a000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x37000) = 0x7b3a00f1a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dbcm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1333400, ...}) = 0 mmap(NULL, 1051904, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00de1000 mmap(0x7b3a00eda000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xf8000) = 0x7b3a00eda000 mmap(0x7b3a00ee0000, 7424, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00ee0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_ihc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=251664, ...}) = 0 mmap(NULL, 175904, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02064000 mprotect(0x7b3a0208c000, 4096, PROT_NONE) = 0 mmap(0x7b3a0208d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x28000) = 0x7b3a0208d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dygr_qdl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2084808, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a04667000 mmap(NULL, 2013682, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00bf5000 mprotect(0x7b3a00d9c000, 4096, PROT_NONE) = 0 mmap(0x7b3a00d9d000, 278528, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a7000) = 0x7b3a00d9d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libprotobuf.so.3.17.3.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0`F\f\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=3503728, ...}) = 0 mmap(NULL, 7072120, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b3a00536000 mmap(0x7b3a00600000, 4974968, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b3a00600000 munmap(0x7b3a00536000, 827392) = 0 munmap(0x7b3a00abf000, 1268088) = 0 mprotect(0x7b3a008b1000, 2093056, PROT_NONE) = 0 mmap(0x7b3a00ab0000, 57344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2b0000) = 0x7b3a00ab0000 mmap(0x7b3a00abe000, 2424, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00abe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libatm_cga.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=296904, ...}) = 0 mmap(NULL, 872152, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00b20000 mmap(0x7b3a00b51000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x30000) = 0x7b3a00b51000 mmap(0x7b3a00b55000, 655064, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00b55000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_factory.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=238120, ...}) = 0 mmap(NULL, 170736, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00af6000 mmap(0x7b3a00b1d000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x26000) = 0x7b3a00b1d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_syn.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=886184, ...}) = 0 mmap(NULL, 679600, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0055a000 mprotect(0x7b3a005e4000, 4096, PROT_NONE) = 0 mmap(0x7b3a005e5000, 110592, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8a000) = 0x7b3a005e5000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_cyclonev.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4741112, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a04665000 mmap(NULL, 4278112, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00000000 mmap(0x7b3a00377000, 638976, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x376000) = 0x7b3a00377000 mmap(0x7b3a00413000, 5984, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00413000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_arriav.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=17743888, ...}) = 0 mmap(NULL, 16204512, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ff000000 mprotect(0x7b39ffca9000, 4096, PROT_NONE) = 0 mmap(0x7b39ffcaa000, 2895872, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xca9000) = 0x7b39ffcaa000 mmap(0x7b39fff6d000, 29408, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fff6d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_nadder.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=9317744, ...}) = 0 mmap(NULL, 8460568, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fe600000 mprotect(0x7b39feca2000, 4096, PROT_NONE) = 0 mmap(0x7b39feca3000, 1486848, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6a2000) = 0x7b39feca3000 mmap(0x7b39fee0e000, 14616, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fee0e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_nightfury.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4820776, ...}) = 0 mmap(NULL, 4295952, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fe000000 mmap(0x7b39fe35c000, 765952, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x35b000) = 0x7b39fe35c000 mmap(0x7b39fe417000, 7440, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fe417000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_dynamic.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=521480, ...}) = 0 mmap(NULL, 331248, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00509000 mmap(0x7b3a00554000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4a000) = 0x7b3a00554000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_stratixv.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=13652248, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a043ac000 mmap(NULL, 12473200, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fd400000 mprotect(0x7b39fddd0000, 4096, PROT_NONE) = 0 mmap(0x7b39fddd1000, 2158592, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9d0000) = 0x7b39fddd1000 mmap(0x7b39fdfe0000, 21360, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fdfe0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_fusion.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4007152, ...}) = 0 mmap(NULL, 3511616, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fd000000 mprotect(0x7b39fd2b6000, 4096, PROT_NONE) = 0 mmap(0x7b39fd2b7000, 659456, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2b6000) = 0x7b39fd2b7000 mmap(0x7b39fd358000, 5440, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fd358000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_cuda.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4487128, ...}) = 0 mmap(NULL, 3976056, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fcc00000 mmap(0x7b39fcf12000, 749568, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x311000) = 0x7b39fcf12000 mmap(0x7b39fcfc9000, 7032, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fcfc9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_titan.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=5635096, ...}) = 0 mmap(NULL, 5053496, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc600000 mmap(0x7b39fc9f2000, 909312, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3f1000) = 0x7b39fc9f2000 mmap(0x7b39fcad0000, 7224, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fcad0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_tgx.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4047640, ...}) = 0 mmap(NULL, 3591504, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc200000 mmap(0x7b39fc4d3000, 626688, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2d2000) = 0x7b39fc4d3000 mmap(0x7b39fc56c000, 3408, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fc56c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_stingray.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1545536, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a043aa000 mmap(NULL, 1277312, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39feec8000 mmap(0x7b39fefca000, 221184, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x101000) = 0x7b39fefca000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_hcx.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=10077016, ...}) = 0 mmap(NULL, 9044168, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb800000 mprotect(0x7b39fbeea000, 4096, PROT_NONE) = 0 mmap(0x7b39fbeeb000, 1773568, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6ea000) = 0x7b39fbeeb000 mmap(0x7b39fc09c000, 16584, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fc09c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_generic.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=483792, ...}) = 0 mmap(NULL, 297232, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a004c0000 mprotect(0x7b3a00502000, 4096, PROT_NONE) = 0 mmap(0x7b3a00503000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x42000) = 0x7b3a00503000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_arm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4202200, ...}) = 0 mmap(NULL, 3692608, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb400000 mprotect(0x7b39fb6e2000, 4096, PROT_NONE) = 0 mmap(0x7b39fb6e3000, 659456, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2e2000) = 0x7b39fb6e3000 mmap(0x7b39fb784000, 6208, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fb784000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_ygr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2485200, ...}) = 0 mmap(NULL, 2123392, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb000000 mprotect(0x7b39fb1ad000, 4096, PROT_NONE) = 0 mmap(0x7b39fb1ae000, 360448, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1ad000) = 0x7b39fb1ae000 mmap(0x7b39fb206000, 1664, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fb206000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2235224, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a043a8000 mmap(NULL, 1745688, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fe455000 mmap(0x7b39fe5de000, 131072, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x188000) = 0x7b39fe5de000 mmap(0x7b39fe5fe000, 4888, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fe5fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dloc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=89920, ...}) = 0 mmap(NULL, 64640, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00ae6000 mmap(0x7b3a00af4000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd000) = 0x7b3a00af4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_db.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=3414088, ...}) = 0 mmap(NULL, 2476465, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fac00000 mmap(0x7b39fadb7000, 512000, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1b6000) = 0x7b39fadb7000 mmap(0x7b39fae34000, 166321, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fae34000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_sgate.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=6847608, ...}) = 0 mmap(NULL, 5598912, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa600000 mprotect(0x7b39fab34000, 4096, PROT_NONE) = 0 mmap(0x7b39fab35000, 114688, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x534000) = 0x7b39fab35000 mmap(0x7b39fab51000, 24256, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fab51000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_idu.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=741256, ...}) = 0 mmap(NULL, 609640, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0042b000 mmap(0x7b3a004bb000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8f000) = 0x7b3a004bb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_rdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1399680, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a043a6000 mmap(NULL, 1069472, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fcafa000 mprotect(0x7b39fcbef000, 4096, PROT_NONE) = 0 mmap(0x7b39fcbf0000, 53248, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xf5000) = 0x7b39fcbf0000 mmap(0x7b39fcbfd000, 8608, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fcbfd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_rstr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=39856, ...}) = 0 mmap(NULL, 29016, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00ade000 mmap(0x7b3a00ae4000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b3a00ae4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_dbmui.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=101096, ...}) = 0 mmap(NULL, 82112, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00ac9000 mmap(0x7b3a00adb000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x11000) = 0x7b3a00adb000 mmap(0x7b3a00add000, 192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b3a00add000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_flow_util.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=83384, ...}) = 0 mmap(NULL, 66680, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a0041a000 mmap(0x7b3a00429000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe000) = 0x7b3a00429000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_kpt.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=780224, ...}) = 0 mmap(NULL, 592208, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fee37000 mmap(0x7b39feec2000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8a000) = 0x7b39feec2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dmgr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=193112, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a043a4000 mmap(NULL, 142536, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fffdd000 mmap(0x7b39ffffe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x20000) = 0x7b39ffffe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dpow.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=690792, ...}) = 0 mmap(NULL, 444048, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fd393000 mprotect(0x7b39fd3fb000, 4096, PROT_NONE) = 0 mmap(0x7b39fd3fc000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x68000) = 0x7b39fd3fc000 mmap(0x7b39fd3ff000, 1680, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fd3ff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dtm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=554552, ...}) = 0 mmap(NULL, 459024, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc58f000 mprotect(0x7b39fc5f8000, 4096, PROT_NONE) = 0 mmap(0x7b39fc5f9000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x69000) = 0x7b39fc5f9000 mmap(0x7b39fc5fe000, 4368, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fc5fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dygr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=5064712, ...}) = 0 mmap(NULL, 4561472, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa000000 mprotect(0x7b39fa409000, 4096, PROT_NONE) = 0 mmap(0x7b39fa40a000, 303104, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x409000) = 0x7b39fa40a000 mmap(0x7b39fa454000, 23104, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fa454000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dmig.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=365688, ...}) = 0 mmap(NULL, 291521, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fff95000 mmap(0x7b39fffd9000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x43000) = 0x7b39fffd9000 mmap(0x7b39fffdb000, 4801, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fffdb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dev.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2394216, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a03a40000 mmap(NULL, 2121528, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9c00000 mmap(0x7b39f9dcc000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1cb000) = 0x7b39f9dcc000 mmap(0x7b39f9dd4000, 204600, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f9dd4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_wys.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=97517072, ...}) = 0 mmap(NULL, 95518056, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f4000000 mmap(0x7b39f94f0000, 4947968, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x54ef000) = 0x7b39f94f0000 mmap(0x7b39f99a8000, 1506664, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f99a8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_definition.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=195072, ...}) = 0 mmap(NULL, 134264, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fee16000 mmap(0x7b39fee34000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d000) = 0x7b39fee34000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_put.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=41976, ...}) = 0 mmap(NULL, 33424, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00ac0000 mmap(0x7b3a00ac7000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b3a00ac7000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libqcl_pllc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=305352, ...}) = 0 mmap(NULL, 261553, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc1c0000 mmap(0x7b39fc1fe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3d000) = 0x7b39fc1fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=555616, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a02afb000 mmap(NULL, 434480, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc155000 mprotect(0x7b39fc1b8000, 4096, PROT_NONE) = 0 mmap(0x7b39fc1b9000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x63000) = 0x7b39fc1b9000 mmap(0x7b39fc1be000, 4400, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fc1be000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_hut.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=37952, ...}) = 0 mmap(NULL, 29224, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fff8d000 mmap(0x7b39fff93000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b39fff93000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_mio.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=184512, ...}) = 0 mmap(NULL, 158096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fe42e000 mmap(0x7b39fe453000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x24000) = 0x7b39fe453000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_hdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=3798520, ...}) = 0 mmap(NULL, 3192305, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f3c00000 mmap(0x7b39f3ef3000, 77824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2f2000) = 0x7b39f3ef3000 mmap(0x7b39f3f06000, 22001, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f3f06000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_qdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=604664, ...}) = 0 mmap(NULL, 470704, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc0e2000 mprotect(0x7b39fc14f000, 4096, PROT_NONE) = 0 mmap(0x7b39fc150000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6d000) = 0x7b39fc150000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_afm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=113480, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b3a02af9000 mmap(NULL, 83576, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fff78000 mprotect(0x7b39fff8a000, 4096, PROT_NONE) = 0 mmap(0x7b39fff8b000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12000) = 0x7b39fff8b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_dbm.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=70360, ...}) = 0 mmap(NULL, 58496, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fe41f000 mmap(0x7b39fe42c000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b39fe42c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_cksum.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=46216, ...}) = 0 mmap(NULL, 37600, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fdff6000 mmap(0x7b39fdffe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39fdffe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_qcu_facade.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=9488, ...}) = 0 mmap(NULL, 8288, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a02061000 mmap(0x7b3a02062000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b3a02062000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libatm_autil.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=19864, ...}) = 0 mmap(NULL, 16720, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b3a00415000 mprotect(0x7b3a00417000, 4096, PROT_NONE) = 0 mmap(0x7b3a00418000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b3a00418000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libatm_astr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=42525560, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fff76000 mmap(NULL, 26618728, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f2200000 mprotect(0x7b39f3963000, 4096, PROT_NONE) = 0 mmap(0x7b39f3964000, 1937408, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1763000) = 0x7b39f3964000 mmap(0x7b39f3b3d000, 154472, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f3b3d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_dyn.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=105656, ...}) = 0 mmap(NULL, 79200, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fd37f000 mprotect(0x7b39fd390000, 4096, PROT_NONE) = 0 mmap(0x7b39fd391000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x11000) = 0x7b39fd391000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcomp_qexe.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=208832, ...}) = 0 mmap(NULL, 175560, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fcfd5000 mmap(0x7b39fcffd000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x27000) = 0x7b39fcffd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_cloud.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=162328, ...}) = 0 mmap(NULL, 124416, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fd360000 mprotect(0x7b39fd37c000, 4096, PROT_NONE) = 0 mmap(0x7b39fd37d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1c000) = 0x7b39fd37d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_curl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=107176, ...}) = 0 mmap(NULL, 91360, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fcae3000 mmap(0x7b39fcaf8000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14000) = 0x7b39fcaf8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_tb2.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14368, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fee14000 mmap(NULL, 12344, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fe41b000 mmap(0x7b39fe41d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fe41d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_acf.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2965896, ...}) = 0 mmap(NULL, 2785264, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1e00000 mmap(0x7b39f2031000, 487424, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x230000) = 0x7b39f2031000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libddb_dstr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=6068944, ...}) = 0 mmap(NULL, 5010136, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1800000 mprotect(0x7b39f1c2a000, 4096, PROT_NONE) = 0 mmap(0x7b39f1c2b000, 569344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x42a000) = 0x7b39f1c2b000 mmap(0x7b39f1cb6000, 70360, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f1cb6000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_dbs.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=3608424, ...}) = 0 mmap(NULL, 3586232, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1400000 mmap(0x7b39f16e9000, 536576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2e8000) = 0x7b39f16e9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_qsym.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=227560, ...}) = 0 mmap(NULL, 186952, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc0b4000 mmap(0x7b39fc0e0000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2b000) = 0x7b39fc0e0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsys_cpt.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1839880, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fee12000 mmap(NULL, 1648312, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb26d000 mprotect(0x7b39fb3db000, 4096, PROT_NONE) = 0 mmap(0x7b39fb3dc000, 106496, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x16e000) = 0x7b39fb3dc000 mmap(0x7b39fb3f6000, 38584, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fb3f6000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_ntfq.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=32024, ...}) = 0 mmap(NULL, 25104, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fdfef000 mmap(0x7b39fdff4000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39fdff4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_ipc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=45816, ...}) = 0 mmap(NULL, 37872, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fcfcb000 mmap(0x7b39fcfd3000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39fcfd3000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_bat.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=128848, ...}) = 0 mmap(NULL, 99296, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc576000 mprotect(0x7b39fc58c000, 4096, PROT_NONE) = 0 mmap(0x7b39fc58d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x16000) = 0x7b39fc58d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_ntf.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=25704, ...}) = 0 mmap(NULL, 20920, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fdfe9000 mmap(0x7b39fdfed000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39fdfed000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_msg.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=999136, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fe419000 mmap(NULL, 988624, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39faf0e000 mprotect(0x7b39fafc1000, 4096, PROT_NONE) = 0 mmap(0x7b39fafc2000, 36864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xb3000) = 0x7b39fafc2000 mmap(0x7b39fafcb000, 214480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fafcb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_xml.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=90136, ...}) = 0 mmap(NULL, 62336, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fcad3000 mprotect(0x7b39fcae0000, 4096, PROT_NONE) = 0 mmap(0x7b39fcae1000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd000) = 0x7b39fcae1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxerces-c-3.2.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\300\4\23\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=22607216, ...}) = 0 mmap(NULL, 7950568, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39f0c6a000 mmap(0x7b39f0e00000, 5853416, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39f0e00000 munmap(0x7b39f0c6a000, 1662976) = 0 munmap(0x7b39f1396000, 430312) = 0 mprotect(0x7b39f115b000, 2097152, PROT_NONE) = 0 mmap(0x7b39f135b000, 237568, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x35b000) = 0x7b39f135b000 mmap(0x7b39f1395000, 232, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f1395000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_sqlite3.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1081352, ...}) = 0 mmap(NULL, 979836, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa510000 mprotect(0x7b39fa5f7000, 4096, PROT_NONE) = 0 mmap(0x7b39fa5f8000, 28672, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe7000) = 0x7b39fa5f8000 mmap(0x7b39fa5ff000, 892, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fa5ff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_interface.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=8496, ...}) = 0 mmap(NULL, 8217, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fdfe6000 mmap(0x7b39fdfe7000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39fdfe7000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_big.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=149368, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fd35e000 mmap(NULL, 126000, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb7e1000 mprotect(0x7b39fb7fd000, 4096, PROT_NONE) = 0 mmap(0x7b39fb7fe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1c000) = 0x7b39fb7fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdb_pdb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=157400, ...}) = 0 mmap(NULL, 128624, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb7c1000 mprotect(0x7b39fb7de000, 4096, PROT_NONE) = 0 mmap(0x7b39fb7df000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d000) = 0x7b39fb7df000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_tst.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=40960, ...}) = 0 mmap(NULL, 33441, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc56d000 mmap(0x7b39fc574000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39fc574000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_clw.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=22360, ...}) = 0 mmap(NULL, 16648, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc0af000 mmap(0x7b39fc0b2000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fc0b2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_atcl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=427000, ...}) = 0 mmap(NULL, 318576, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb21f000 mmap(0x7b39fb268000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x48000) = 0x7b39fb268000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_fstr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=185280, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fd35c000 mmap(NULL, 137384, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb79f000 mprotect(0x7b39fb7bb000, 4096, PROT_NONE) = 0 mmap(0x7b39fb7bc000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1c000) = 0x7b39fb7bc000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_qtl.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=296744, ...}) = 0 mmap(NULL, 236104, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39faed4000 mmap(0x7b39faf08000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x33000) = 0x7b39faf08000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_cfg_ini.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=197560, ...}) = 0 mmap(NULL, 181216, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39faea7000 mprotect(0x7b39faecc000, 4096, PROT_NONE) = 0 mmap(0x7b39faecd000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x25000) = 0x7b39faecd000 mmap(0x7b39faed3000, 992, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39faed3000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_zlib.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=173944, ...}) = 0 mmap(NULL, 164200, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fae7e000 mmap(0x7b39faea5000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x26000) = 0x7b39faea5000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_gen.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=533920, ...}) = 0 mmap(NULL, 441256, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fab94000 mmap(0x7b39fabfc000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x67000) = 0x7b39fabfc000 mmap(0x7b39fabff000, 2984, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fabff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_fio.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=216248, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fd35a000 mmap(NULL, 185952, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fab66000 mmap(0x7b39fab8e000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x27000) = 0x7b39fab8e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_mem.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=175192, ...}) = 0 mmap(NULL, 141785, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa4ed000 mmap(0x7b39fa50e000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x20000) = 0x7b39fa50e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_err.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=882760, ...}) = 0 mmap(NULL, 189028, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa4be000 mprotect(0x7b39fa4df000, 4096, PROT_NONE) = 0 mmap(0x7b39fa4e0000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x21000) = 0x7b39fa4e0000 mmap(0x7b39fa4e2000, 41572, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fa4e2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_ver.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=45008, ...}) = 0 mmap(NULL, 37840, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fc0a5000 mmap(0x7b39fc0ad000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39fc0ad000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libccl_thr.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=84048, ...}) = 0 mmap(NULL, 216601, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa489000 mmap(0x7b39fa498000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe000) = 0x7b39fa498000 mmap(0x7b39fa49a000, 146969, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fa49a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Test.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\5\1\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=439144, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fc0a3000 mmap(NULL, 364544, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9fa7000 mprotect(0x7b39f9fb6000, 274432, PROT_NONE) = 0 mmap(0x7b39f9fb6000, 196608, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xf000) = 0x7b39f9fb6000 mmap(0x7b39f9fe6000, 73728, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3f000) = 0x7b39f9fe6000 mmap(0x7b39f9ff9000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x51000) = 0x7b39f9ff9000 mmap(0x7b39f9ffc000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f9ffc000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Qml.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\320I\n\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=6067968, ...}) = 0 mmap(NULL, 4927320, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f0800000 mprotect(0x7b39f08a1000, 4145152, PROT_NONE) = 0 mmap(0x7b39f08a1000, 3305472, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa1000) = 0x7b39f08a1000 mmap(0x7b39f0bc8000, 835584, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3c8000) = 0x7b39f0bc8000 mmap(0x7b39f0c95000, 114688, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x494000) = 0x7b39f0c95000 mmap(0x7b39f0cb1000, 8024, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f0cb1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Network.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\372\2\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=1642616, ...}) = 0 mmap(NULL, 1307936, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9e67000 mmap(0x7b39f9e94000, 851968, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2d000) = 0x7b39f9e94000 mmap(0x7b39f9f64000, 241664, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xfd000) = 0x7b39f9f64000 mmap(0x7b39f9f9f000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x137000) = 0x7b39f9f9f000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Widgets.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0Pi\25\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=8311896, ...}) = 0 mmap(NULL, 6891304, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f0000000 mprotect(0x7b39f014e000, 5324800, PROT_NONE) = 0 mmap(0x7b39f014e000, 3907584, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14e000) = 0x7b39f014e000 mmap(0x7b39f0508000, 1413120, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x508000) = 0x7b39f0508000 mmap(0x7b39f0662000, 200704, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x661000) = 0x7b39f0662000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Gui.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\36\f\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=8392960, ...}) = 0 mmap(NULL, 7303344, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ef800000 mmap(0x7b39ef8be000, 5394432, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xbe000) = 0x7b39ef8be000 mmap(0x7b39efde3000, 1007616, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5e3000) = 0x7b39efde3000 mmap(0x7b39efed9000, 81920, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6d8000) = 0x7b39efed9000 mmap(0x7b39efeed000, 41136, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39efeed000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Core.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\340\206\f\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=8046456, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fc0a1000 mmap(NULL, 7030344, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ef000000 mmap(0x7b39ef095000, 3608576, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x95000) = 0x7b39ef095000 mmap(0x7b39ef406000, 2732032, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x406000) = 0x7b39ef406000 mmap(0x7b39ef6a1000, 65536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6a0000) = 0x7b39ef6a1000 mmap(0x7b39ef6b1000, 13896, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39ef6b1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libboost_regex-x64.so.1.70.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@\344\1\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1092331, ...}) = 0 mmap(NULL, 5040248, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39eeb31000 mmap(0x7b39eec00000, 2943096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39eec00000 munmap(0x7b39eeb31000, 847872) = 0 munmap(0x7b39eeecf000, 1247352) = 0 mprotect(0x7b39eecca000, 2093056, PROT_NONE) = 0 mmap(0x7b39eeec9000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc9000) = 0x7b39eeec9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libboost_serialization-x64.so.1.70.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0000|\1\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=492232, ...}) = 0 mmap(NULL, 4496280, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39ee7b6000 mmap(0x7b39ee800000, 2399128, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ee800000 munmap(0x7b39ee7b6000, 303104) = 0 munmap(0x7b39eea4a000, 1792920) = 0 mprotect(0x7b39ee847000, 2093056, PROT_NONE) = 0 mmap(0x7b39eea46000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x46000) = 0x7b39eea46000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libboost_filesystem-x64.so.1.70.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\300d\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=124707, ...}) = 0 mmap(NULL, 4291440, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39ee3e8000 mmap(0x7b39ee400000, 2194288, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ee400000 munmap(0x7b39ee3e8000, 98304) = 0 munmap(0x7b39ee618000, 1997680) = 0 mprotect(0x7b39ee417000, 2097152, PROT_NONE) = 0 mmap(0x7b39ee617000, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x17000) = 0x7b39ee617000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libboost_system-x64.so.1.70.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@\5\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=6197, ...}) = 0 mmap(NULL, 4196608, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39edfff000 mmap(0x7b39ee000000, 2099456, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ee000000 munmap(0x7b39edfff000, 4096) = 0 munmap(0x7b39ee201000, 2091264) = 0 mprotect(0x7b39ee001000, 2093056, PROT_NONE) = 0 mmap(0x7b39ee200000, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ee200000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libboost_program_options-x64.so.1.70.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0P\245\2\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=590683, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb79d000 mmap(NULL, 4636184, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39edb94000 mmap(0x7b39edc00000, 2539032, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39edc00000 munmap(0x7b39edb94000, 442368) = 0 munmap(0x7b39ede6c000, 1654296) = 0 mprotect(0x7b39edc66000, 2097152, PROT_NONE) = 0 mmap(0x7b39ede66000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x66000) = 0x7b39ede66000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libboost_unit_test_framework-x64.so.1.70.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\300\307\2\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=966430, ...}) = 0 mmap(NULL, 4928064, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39ed74c000 mmap(0x7b39ed800000, 2830912, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ed800000 munmap(0x7b39ed74c000, 737280) = 0 munmap(0x7b39edab4000, 1356352) = 0 mprotect(0x7b39ed8ac000, 2093056, PROT_NONE) = 0 mmap(0x7b39edaab000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xab000) = 0x7b39edaab000 mmap(0x7b39edab1000, 8768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39edab1000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libSafeString.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\20\31\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=70640, ...}) = 0 mmap(NULL, 4254440, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39ed3f1000 mmap(0x7b39ed400000, 2157288, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ed400000 munmap(0x7b39ed3f1000, 61440) = 0 munmap(0x7b39ed60f000, 2034408) = 0 mprotect(0x7b39ed40f000, 2093056, PROT_NONE) = 0 mmap(0x7b39ed60e000, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe000) = 0x7b39ed60e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtbbamalloc.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@\20\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=20352, ...}) = 0 mmap(NULL, 16432, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb798000 mmap(0x7b39fb799000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb799000 mmap(0x7b39fb79a000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb79a000 mmap(0x7b39fb79b000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb79b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtbbmalloc.so.2", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0S\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1087776, ...}) = 0 mmap(NULL, 3288320, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ed000000 mmap(0x7b39ed005000, 57344, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b39ed005000 mmap(0x7b39ed013000, 28672, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x13000) = 0x7b39ed013000 mmap(0x7b39ed01a000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x19000) = 0x7b39ed01a000 mmap(0x7b39ed01d000, 3169536, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39ed01d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtbb.so.2", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\340\350\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=3758448, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb796000 mmap(NULL, 254920, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9e28000 mmap(0x7b39f9e36000, 118784, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe000) = 0x7b39f9e36000 mmap(0x7b39f9e53000, 53248, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2b000) = 0x7b39f9e53000 mmap(0x7b39f9e60000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x37000) = 0x7b39f9e60000 mmap(0x7b39f9e64000, 9160, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f9e64000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5PrintSupport.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0 $\2\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=529648, ...}) = 0 mmap(NULL, 409824, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9b9b000 mprotect(0x7b39f9bbb000, 262144, PROT_NONE) = 0 mmap(0x7b39f9bbb000, 176128, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x20000) = 0x7b39f9bbb000 mmap(0x7b39f9be6000, 81920, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4b000) = 0x7b39f9be6000 mmap(0x7b39f9bfb000, 20480, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5f000) = 0x7b39f9bfb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5Sql.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0p\32\1\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=379104, ...}) = 0 mmap(NULL, 315816, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9b4d000 mprotect(0x7b39f9b5e000, 237568, PROT_NONE) = 0 mmap(0x7b39f9b5e000, 196608, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x11000) = 0x7b39f9b5e000 mmap(0x7b39f9b8e000, 36864, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x41000) = 0x7b39f9b8e000 mmap(0x7b39f9b98000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4a000) = 0x7b39f9b98000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtcl8.6.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0pw\3\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1839856, ...}) = 0 mmap(NULL, 1713968, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39eea5d000 mmap(0x7b39eea90000, 1196032, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x33000) = 0x7b39eea90000 mmap(0x7b39eebb4000, 237568, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x157000) = 0x7b39eebb4000 mmap(0x7b39eebee000, 69632, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x190000) = 0x7b39eebee000 mmap(0x7b39eebff000, 1840, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39eebff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libicudata.so.69", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\36\2\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=28666384, ...}) = 0 mmap(NULL, 32859584, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39eb0a9000 mmap(0x7b39eb200000, 30762432, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39eb200000 munmap(0x7b39eb0a9000, 1404928) = 0 munmap(0x7b39ecf57000, 689600) = 0 mprotect(0x7b39ecd57000, 2093056, PROT_NONE) = 0 mmap(0x7b39ecf56000, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1b56000) = 0x7b39ecf56000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libicuuc.so.69", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\300d\6\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2462448, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb794000 mmap(NULL, 6335120, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39eabf5000 mmap(0x7b39eac00000, 4237968, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39eac00000 munmap(0x7b39eabf5000, 45056) = 0 munmap(0x7b39eb00b000, 2050704) = 0 mprotect(0x7b39eadf7000, 2093056, PROT_NONE) = 0 mmap(0x7b39eaff6000, 77824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1f6000) = 0x7b39eaff6000 mmap(0x7b39eb009000, 6800, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39eb009000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libnsl.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=131979, ...}) = 0 mmap(NULL, 131979, PROT_READ, MAP_PRIVATE, 3, 0) = 0x7b39fae5d000 close(3) = 0 openat(AT_FDCWD, "/usr/lib/libnsl.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=92176, ...}) = 0 mmap(NULL, 104024, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fa46f000 mmap(0x7b39fa473000, 57344, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39fa473000 mmap(0x7b39fa481000, 16384, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12000) = 0x7b39fa481000 mmap(0x7b39fa485000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x15000) = 0x7b39fa485000 mmap(0x7b39fa487000, 5720, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39fa487000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/librt.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/librt.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14352, ...}) = 0 mmap(NULL, 16400, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb78f000 mmap(0x7b39fb790000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb790000 mmap(0x7b39fb791000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb791000 mmap(0x7b39fb792000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb792000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libpthread.so.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libpthread.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14288, ...}) = 0 mmap(NULL, 16400, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb78a000 mmap(0x7b39fb78b000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb78b000 mmap(0x7b39fb78c000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb78c000 mmap(0x7b39fb78d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb78d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdl.so.2", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libdl.so.2", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14280, ...}) = 0 mmap(NULL, 16400, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb21a000 mmap(0x7b39fb21b000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb21b000 mmap(0x7b39fb21c000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb21c000 mmap(0x7b39fb21d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb21d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libtbbmalloc_proxy.so.2", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0 \21\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=80784, ...}) = 0 mmap(NULL, 16600, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb215000 mmap(0x7b39fb216000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb216000 mmap(0x7b39fb217000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb217000 mmap(0x7b39fb218000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb218000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libstdc++.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0p\237\t\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=22543592, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb788000 mmap(NULL, 1938912, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ee626000 mmap(0x7b39ee6bc000, 954368, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x96000) = 0x7b39ee6bc000 mmap(0x7b39ee7a5000, 303104, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x17f000) = 0x7b39ee7a5000 mmap(0x7b39ee7ef000, 57344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1c8000) = 0x7b39ee7ef000 mmap(0x7b39ee7fd000, 9696, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39ee7fd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libm.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libm.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=973144, ...}) = 0 mmap(NULL, 975176, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f3f11000 mmap(0x7b39f3f1f000, 536576, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe000) = 0x7b39f3f1f000 mmap(0x7b39f3fa2000, 376832, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x91000) = 0x7b39f3fa2000 mmap(0x7b39f3ffe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xec000) = 0x7b39f3ffe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgomp.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\340\226\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1474456, ...}) = 0 mmap(NULL, 227312, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f3bc8000 mmap(0x7b39f3bd1000, 143360, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9000) = 0x7b39f3bd1000 mmap(0x7b39f3bf4000, 40960, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2c000) = 0x7b39f3bf4000 mmap(0x7b39f3bfe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x35000) = 0x7b39f3bfe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgcc_s.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0003\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=881600, ...}) = 0 mmap(NULL, 103504, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9e0e000 mmap(0x7b39f9e11000, 69632, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f9e11000 mmap(0x7b39f9e22000, 16384, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14000) = 0x7b39f9e22000 mmap(0x7b39f9e26000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x17000) = 0x7b39f9e26000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libc.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\340_\2\0\0\0\0\0"..., 832) = 832 pread64(3, "\6\0\0\0\4\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0"..., 784, 64) = 784 fstat(3, {st_mode=S_IFREG|0755, st_size=2014520, ...}) = 0 pread64(3, "\6\0\0\0\4\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0@\0\0\0\0\0\0\0"..., 784, 64) = 784 mmap(NULL, 2034616, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ee20f000 mmap(0x7b39ee233000, 1511424, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x24000) = 0x7b39ee233000 mmap(0x7b39ee3a4000, 319488, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x195000) = 0x7b39ee3a4000 mmap(0x7b39ee3f2000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1e3000) = 0x7b39ee3f2000 mmap(0x7b39ee3f8000, 31672, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39ee3f8000 close(3) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb786000 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libpython3.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@\20\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=16168, ...}) = 0 mmap(NULL, 16424, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb210000 mmap(0x7b39fb211000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb211000 mmap(0x7b39fb212000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb212000 mmap(0x7b39fb213000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb213000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libutil.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libutil.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14280, ...}) = 0 mmap(NULL, 16400, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fb20b000 mmap(0x7b39fb20c000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fb20c000 mmap(0x7b39fb20d000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb20d000 mmap(0x7b39fb20e000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fb20e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libpython3.8.so.1.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\320\247\6\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=13234280, ...}) = 0 mmap(NULL, 3494136, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ea800000 mprotect(0x7b39ea864000, 2691072, PROT_NONE) = 0 mmap(0x7b39ea864000, 1720320, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x64000) = 0x7b39ea864000 mmap(0x7b39eaa08000, 966656, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x208000) = 0x7b39eaa08000 mmap(0x7b39eaaf5000, 262144, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2f4000) = 0x7b39eaaf5000 mmap(0x7b39eab35000, 131320, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39eab35000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcurl.so.4", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0 \347\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=690599, ...}) = 0 mmap(NULL, 4804472, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39ea36b000 mmap(0x7b39ea400000, 2707320, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ea400000 munmap(0x7b39ea36b000, 610304) = 0 munmap(0x7b39ea695000, 1486712) = 0 mprotect(0x7b39ea490000, 2093056, PROT_NONE) = 0 mmap(0x7b39ea68f000, 24576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8f000) = 0x7b39ea68f000 close(3) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb209000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fb207000 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libz.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0 3\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=126312, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fab64000 mmap(NULL, 119192, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9b2f000 mmap(0x7b39f9b32000, 73728, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f9b32000 mmap(0x7b39f9b44000, 28672, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x15000) = 0x7b39f9b44000 mmap(0x7b39f9b4b000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1b000) = 0x7b39f9b4b000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/liblzma.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@)\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=588974, ...}) = 0 mmap(NULL, 2235952, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39ea1de000 mmap(0x7b39ea200000, 1187376, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39ea200000 munmap(0x7b39ea1de000, 139264) = 0 munmap(0x7b39ea322000, 908848) = 0 mprotect(0x7b39ea222000, 1044480, PROT_NONE) = 0 mmap(0x7b39ea321000, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x21000) = 0x7b39ea321000 close(3) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fab62000 openat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/glibc-hwcaps/x86-64-v4/libicui18n.so.69", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/glibc-hwcaps/x86-64-v4/", 0x7ffec5846a50, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/glibc-hwcaps/x86-64-v3/libicui18n.so.69", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/glibc-hwcaps/x86-64-v3/", 0x7ffec5846a50, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/glibc-hwcaps/x86-64-v2/libicui18n.so.69", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/glibc-hwcaps/x86-64-v2/", 0x7ffec5846a50, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/libicui18n.so.69", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/nfs/site/disks/psg_ctools_1/gcc/7.2.0/1/linux64/bin/../lib/gcc/x86_64-redhat-linux/7.2.0/../../../../lib64/", 0x7ffec5846a50, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libicui18n.so.69", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\300\"\17\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=4170192, ...}) = 0 mmap(NULL, 7537848, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_DENYWRITE, -1, 0) = 0x7b39e9acf000 mmap(0x7b39e9c00000, 5440696, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0) = 0x7b39e9c00000 munmap(0x7b39e9acf000, 1249280) = 0 munmap(0x7b39ea131000, 844984) = 0 mprotect(0x7b39e9f20000, 2093056, PROT_NONE) = 0 mmap(0x7b39ea11f000, 69632, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x31f000) = 0x7b39ea11f000 mmap(0x7b39ea130000, 1208, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39ea130000 close(3) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fab60000 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgthread-2.0.so.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libgthread-2.0.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14056, ...}) = 0 mmap(NULL, 16400, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fab5b000 mmap(0x7b39fab5c000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fab5c000 mmap(0x7b39fab5d000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fab5d000 mmap(0x7b39fab5e000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fab5e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libglib-2.0.so.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libglib-2.0.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1371512, ...}) = 0 mmap(NULL, 1372744, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f20b0000 mmap(0x7b39f20ce000, 679936, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1e000) = 0x7b39f20ce000 mmap(0x7b39f2174000, 561152, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc4000) = 0x7b39f2174000 mmap(0x7b39f21fd000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14d000) = 0x7b39f21fd000 mmap(0x7b39f21ff000, 584, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f21ff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcrypt.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libcrypt.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=178200, ...}) = 0 mmap(NULL, 209312, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f3b94000 mmap(0x7b39f3b95000, 69632, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39f3b95000 mmap(0x7b39f3ba6000, 98304, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12000) = 0x7b39f3ba6000 mmap(0x7b39f3bbe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2a000) = 0x7b39f3bbe000 mmap(0x7b39f3bc0000, 29088, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f3bc0000 close(3) = 0 openat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/glibc-hwcaps/x86-64-v4/libssl.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/glibc-hwcaps/x86-64-v4/", 0x7ffec58469d0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/glibc-hwcaps/x86-64-v3/libssl.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/glibc-hwcaps/x86-64-v3/", 0x7ffec58469d0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/glibc-hwcaps/x86-64-v2/libssl.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/glibc-hwcaps/x86-64-v2/", 0x7ffec58469d0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/libssl.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/usr/intel/pkgs/gcc/4.7.2/lib64/", 0x7ffec58469d0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libssl.so.3", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=771960, ...}) = 0 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fab59000 mmap(NULL, 677912, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1d5a000 mmap(0x7b39f1df2000, 57344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x97000) = 0x7b39f1df2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcrypto.so.3", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=5278480, ...}) = 0 mmap(NULL, 4673152, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39e9600000 mmap(0x7b39e9a14000, 385024, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x414000) = 0x7b39e9a14000 mmap(0x7b39e9a72000, 11904, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39e9a72000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libpcre2-8.so.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libpcre2-8.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=645072, ...}) = 0 mmap(NULL, 647416, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f0d61000 mmap(0x7b39f0d63000, 466944, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f0d63000 mmap(0x7b39f0dd5000, 167936, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x74000) = 0x7b39f0dd5000 mmap(0x7b39f0dfe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9c000) = 0x7b39f0dfe000 close(3) = 0 mmap(NULL, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa46c000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fab57000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa46a000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa468000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa466000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa464000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa462000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa460000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa45e000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa45c000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39fa45a000 mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39f9e0c000 arch_prctl(ARCH_SET_FS, 0x7b39fa45b680) = 0 set_tid_address(0x7b39fa45b950) = 375096 set_robust_list(0x7b39fa45b960, 24) = 0 rseq(0x7b39fa45bfa0, 0x20, 0, 0x53053053) = 0 mprotect(0x7b39ee3f2000, 16384, PROT_READ) = 0 mprotect(0x7b39f0dfe000, 4096, PROT_READ) = 0 mprotect(0x7b39fb21d000, 4096, PROT_READ) = 0 mprotect(0x7b39fb78d000, 4096, PROT_READ) = 0 mprotect(0x7b39e9a14000, 372736, PROT_READ) = 0 mprotect(0x7b39f1df2000, 36864, PROT_READ) = 0 mprotect(0x7b39f3bbe000, 4096, PROT_READ) = 0 mprotect(0x7b39f21fd000, 4096, PROT_READ) = 0 mprotect(0x7b39fab5e000, 4096, PROT_READ) = 0 mprotect(0x7b39f3ffe000, 4096, PROT_READ) = 0 mprotect(0x7b39f9e26000, 4096, PROT_READ) = 0 mprotect(0x7b39ee7ef000, 45056, PROT_READ) = 0 mprotect(0x7b39f9b4b000, 4096, PROT_READ) = 0 mprotect(0x7b39fb20e000, 4096, PROT_READ) = 0 mprotect(0x7b39eaaf5000, 20480, PROT_READ) = 0 mprotect(0x7b39fb213000, 4096, PROT_READ) = 0 mprotect(0x7b39fb792000, 4096, PROT_READ) = 0 mprotect(0x7b39f3bfe000, 4096, PROT_READ) = 0 mprotect(0x7b39fb79b000, 4096, PROT_READ) = 0 mprotect(0x7b39ed01a000, 4096, PROT_READ) = 0 mprotect(0x7b39fb218000, 4096, PROT_READ) = 0 mprotect(0x7b39fa485000, 4096, PROT_READ) = 0 mprotect(0x7b39eebee000, 57344, PROT_READ) = 0 mprotect(0x7b39ef6a1000, 61440, PROT_READ) = 0 mprotect(0x7b39f9b98000, 8192, PROT_READ) = 0 mprotect(0x7b39efed9000, 69632, PROT_READ) = 0 mprotect(0x7b39f0662000, 196608, PROT_READ) = 0 mprotect(0x7b39f9bfb000, 16384, PROT_READ) = 0 mprotect(0x7b39f9e60000, 8192, PROT_READ) = 0 mmap(NULL, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39f9e09000 mprotect(0x7b39f9f9f000, 28672, PROT_READ) = 0 mprotect(0x7b39f0c95000, 110592, PROT_READ) = 0 mprotect(0x7b39f9ff9000, 8192, PROT_READ) = 0 mprotect(0x7b39fa498000, 4096, PROT_READ) = 0 mprotect(0x7b39fc0ad000, 4096, PROT_READ) = 0 mprotect(0x7b39fa4e0000, 4096, PROT_READ) = 0 mprotect(0x7b39fa50e000, 4096, PROT_READ) = 0 mprotect(0x7b39fab8e000, 4096, PROT_READ) = 0 mprotect(0x7b39fabfc000, 8192, PROT_READ) = 0 mprotect(0x7b39faea5000, 4096, PROT_READ) = 0 mprotect(0x7b39faecd000, 4096, PROT_READ) = 0 mprotect(0x7b39faf08000, 8192, PROT_READ) = 0 mprotect(0x7b39fb7bc000, 16384, PROT_READ) = 0 mprotect(0x7b39fb268000, 12288, PROT_READ) = 0 mprotect(0x7b39fc0b2000, 4096, PROT_READ) = 0 mprotect(0x7b39fc574000, 4096, PROT_READ) = 0 mprotect(0x7b39fb7df000, 4096, PROT_READ) = 0 mprotect(0x7b39fb7fe000, 4096, PROT_READ) = 0 mprotect(0x7b39fdfe7000, 4096, PROT_READ) = 0 mprotect(0x7b39fa5f8000, 12288, PROT_READ) = 0 mprotect(0x7b39f135b000, 77824, PROT_READ) = 0 mprotect(0x7b39fcae1000, 4096, PROT_READ) = 0 mprotect(0x7b39fafc2000, 24576, PROT_READ) = 0 mprotect(0x7b39fdfed000, 4096, PROT_READ) = 0 mprotect(0x7b39fc58d000, 4096, PROT_READ) = 0 mprotect(0x7b39fcfd3000, 4096, PROT_READ) = 0 mprotect(0x7b39fdff4000, 4096, PROT_READ) = 0 mprotect(0x7b39fb3dc000, 32768, PROT_READ) = 0 mprotect(0x7b39fc0e0000, 4096, PROT_READ) = 0 mprotect(0x7b39f16e9000, 499712, PROT_READ) = 0 mprotect(0x7b39f1c2b000, 565248, PROT_READ) = 0 mprotect(0x7b39f2031000, 303104, PROT_READ) = 0 mprotect(0x7b39fe41d000, 4096, PROT_READ) = 0 mprotect(0x7b39fcaf8000, 4096, PROT_READ) = 0 mprotect(0x7b39fd37d000, 4096, PROT_READ) = 0 mprotect(0x7b39fcffd000, 8192, PROT_READ) = 0 mprotect(0x7b39fd391000, 4096, PROT_READ) = 0 mprotect(0x7b39f3964000, 1720320, PROT_READ) = 0 mprotect(0x7b3a00418000, 4096, PROT_READ) = 0 mprotect(0x7b3a02062000, 4096, PROT_READ) = 0 mprotect(0x7b39fdffe000, 4096, PROT_READ) = 0 mprotect(0x7b39fe42c000, 4096, PROT_READ) = 0 mprotect(0x7b39fff8b000, 4096, PROT_READ) = 0 mprotect(0x7b39fc150000, 12288, PROT_READ) = 0 mprotect(0x7b39f3ef3000, 36864, PROT_READ) = 0 mprotect(0x7b39fe453000, 4096, PROT_READ) = 0 mprotect(0x7b39fff93000, 4096, PROT_READ) = 0 mprotect(0x7b39fc1b9000, 8192, PROT_READ) = 0 mprotect(0x7b39fc1fe000, 4096, PROT_READ) = 0 mprotect(0x7b3a00ac7000, 4096, PROT_READ) = 0 mprotect(0x7b39fee34000, 8192, PROT_READ) = 0 mprotect(0x7b39f94f0000, 4132864, PROT_READ) = 0 mprotect(0x7b39f9dcc000, 16384, PROT_READ) = 0 mprotect(0x7b39fffd9000, 4096, PROT_READ) = 0 mprotect(0x7b39fa40a000, 49152, PROT_READ) = 0 mprotect(0x7b39fc5f9000, 16384, PROT_READ) = 0 mprotect(0x7b39fd3fc000, 4096, PROT_READ) = 0 mprotect(0x7b39ffffe000, 4096, PROT_READ) = 0 mprotect(0x7b39feec2000, 16384, PROT_READ) = 0 mprotect(0x7b3a00429000, 4096, PROT_READ) = 0 mprotect(0x7b3a00adb000, 4096, PROT_READ) = 0 mprotect(0x7b3a00ae4000, 4096, PROT_READ) = 0 mprotect(0x7b39fcbf0000, 45056, PROT_READ) = 0 mprotect(0x7b3a004bb000, 8192, PROT_READ) = 0 mprotect(0x7b39fab35000, 86016, PROT_READ) = 0 mprotect(0x7b39fadb7000, 503808, PROT_READ) = 0 mprotect(0x7b3a00af4000, 4096, PROT_READ) = 0 mprotect(0x7b39fe5de000, 86016, PROT_READ) = 0 mprotect(0x7b39fb1ae000, 348160, PROT_READ) = 0 mprotect(0x7b39fb6e3000, 643072, PROT_READ) = 0 mprotect(0x7b3a00503000, 20480, PROT_READ) = 0 mprotect(0x7b39fbeeb000, 1736704, PROT_READ) = 0 mprotect(0x7b39fefca000, 212992, PROT_READ) = 0 mprotect(0x7b39fc4d3000, 610304, PROT_READ) = 0 mprotect(0x7b39fc9f2000, 888832, PROT_READ) = 0 mprotect(0x7b39fcf12000, 733184, PROT_READ) = 0 mprotect(0x7b39fd2b7000, 643072, PROT_READ) = 0 mprotect(0x7b39fddd1000, 2117632, PROT_READ) = 0 mprotect(0x7b3a00554000, 20480, PROT_READ) = 0 mprotect(0x7b39fe35c000, 749568, PROT_READ) = 0 mprotect(0x7b39feca3000, 1458176, PROT_READ) = 0 mprotect(0x7b39ffcaa000, 2842624, PROT_READ) = 0 mprotect(0x7b3a00377000, 626688, PROT_READ) = 0 mprotect(0x7b3a005e5000, 106496, PROT_READ) = 0 mprotect(0x7b3a00b1d000, 4096, PROT_READ) = 0 mprotect(0x7b3a00b51000, 12288, PROT_READ) = 0 mprotect(0x7b3a00ab0000, 32768, PROT_READ) = 0 mprotect(0x7b3a00d9d000, 36864, PROT_READ) = 0 mprotect(0x7b3a0208d000, 4096, PROT_READ) = 0 mprotect(0x7b3a00eda000, 16384, PROT_READ) = 0 mprotect(0x7b3a00f1a000, 4096, PROT_READ) = 0 mprotect(0x7b3a02b24000, 4096, PROT_READ) = 0 mprotect(0x7b3a00f4a000, 4096, PROT_READ) = 0 mprotect(0x7b3a00ff5000, 28672, PROT_READ) = 0 mprotect(0x7b3a020c5000, 8192, PROT_READ) = 0 mprotect(0x7b3a043c2000, 4096, PROT_READ) = 0 mprotect(0x7b3a02117000, 4096, PROT_READ) = 0 mprotect(0x7b3a02b6c000, 4096, PROT_READ) = 0 mprotect(0x7b3a043cd000, 4096, PROT_READ) = 0 mprotect(0x7b3a02030000, 32768, PROT_READ) = 0 mprotect(0x7b3a021fc000, 4096, PROT_READ) = 0 mprotect(0x7b3a02c3e000, 4096, PROT_READ) = 0 mprotect(0x7b3a02add000, 20480, PROT_READ) = 0 mprotect(0x7b3a03a91000, 4096, PROT_READ) = 0 mprotect(0x7b3a02c9c000, 4096, PROT_READ) = 0 mprotect(0x7b3a043fe000, 4096, PROT_READ) = 0 mprotect(0x7b3a04671000, 4096, PROT_READ) = 0 mprotect(0x7b3a02df7000, 24576, PROT_READ) = 0 mprotect(0x7b3a0467d000, 4096, PROT_READ) = 0 mprotect(0x7b3a0468d000, 8192, PROT_READ) = 0 mprotect(0x7b3a04692000, 4096, PROT_READ) = 0 mprotect(0x7b3a03b45000, 4096, PROT_READ) = 0 mprotect(0x7b3a04699000, 4096, PROT_READ) = 0 mprotect(0x7b3a03bf7000, 4096, PROT_READ) = 0 mprotect(0x7b3a04740000, 4096, PROT_READ) = 0 mprotect(0x7b3a04770000, 4096, PROT_READ) = 0 mprotect(0x7b3a04778000, 4096, PROT_READ) = 0 mprotect(0x7b3a039fa000, 98304, PROT_READ) = 0 mprotect(0x7b3a04cdf000, 32768, PROT_READ) = 0 mprotect(0x7b3a042bd000, 4096, PROT_READ) = 0 mprotect(0x7b3a04658000, 28672, PROT_READ) = 0 mprotect(0x7b3a047fc000, 4096, PROT_READ) = 0 mprotect(0x7b3a04d03000, 4096, PROT_READ) = 0 mprotect(0x7b3a04d35000, 8192, PROT_READ) = 0 mprotect(0x7b3a04d79000, 4096, PROT_READ) = 0 mprotect(0x7b3a07bde000, 4096, PROT_READ) = 0 mprotect(0x7b3a04da1000, 8192, PROT_READ) = 0 mprotect(0x7b3a04dbc000, 4096, PROT_READ) = 0 mprotect(0x7b3a04c7b000, 24576, PROT_READ) = 0 mprotect(0x7b3a04e94000, 8192, PROT_READ) = 0 mprotect(0x7b3a04f3b000, 16384, PROT_READ) = 0 mprotect(0x7b3a04f5e000, 4096, PROT_READ) = 0 mprotect(0x7b3a04ff3000, 8192, PROT_READ) = 0 mprotect(0x7b3a051d7000, 16384, PROT_READ) = 0 mprotect(0x7b3a052b2000, 12288, PROT_READ) = 0 mprotect(0x7b3a05bac000, 4096, PROT_READ) = 0 mprotect(0x7b3a053df000, 8192, PROT_READ) = 0 mprotect(0x7b3a05573000, 20480, PROT_READ) = 0 mprotect(0x7b3a05bb5000, 4096, PROT_READ) = 0 mprotect(0x7b3a05bd8000, 4096, PROT_READ) = 0 mprotect(0x7b3a05654000, 32768, PROT_READ) = 0 mprotect(0x7b3a0569f000, 8192, PROT_READ) = 0 mprotect(0x7b3a06e90000, 4096, PROT_READ) = 0 mprotect(0x7b3a05740000, 8192, PROT_READ) = 0 mprotect(0x7b3a057f1000, 8192, PROT_READ) = 0 mprotect(0x7b3a06e95000, 4096, PROT_READ) = 0 mprotect(0x7b3a05c2a000, 8192, PROT_READ) = 0 mprotect(0x7b3a05c57000, 4096, PROT_READ) = 0 mprotect(0x7b3a05c77000, 4096, PROT_READ) = 0 mprotect(0x7b3a05b81000, 12288, PROT_READ) = 0 mprotect(0x7b3a05cd9000, 4096, PROT_READ) = 0 mprotect(0x7b3a096b8000, 4096, PROT_READ) = 0 mprotect(0x7b3a089c1000, 4096, PROT_READ) = 0 mprotect(0x7b3a05e27000, 12288, PROT_READ) = 0 mprotect(0x7b3a06bf6000, 24576, PROT_READ) = 0 mprotect(0x7b3a05fd9000, 114688, PROT_READ) = 0 mprotect(0x7b3a060e0000, 12288, PROT_READ) = 0 mprotect(0x7b3a07bfe000, 4096, PROT_READ) = 0 mprotect(0x7b3a07f72000, 4096, PROT_READ) = 0 mprotect(0x7b3a061fa000, 12288, PROT_READ) = 0 mprotect(0x7b3a06ad9000, 679936, PROT_READ) = 0 mprotect(0x7b3a06f6e000, 20480, PROT_READ) = 0 mprotect(0x7b3a07041000, 8192, PROT_READ) = 0 mprotect(0x7b3a07fa9000, 8192, PROT_READ) = 0 mprotect(0x7b3a089d9000, 4096, PROT_READ) = 0 mprotect(0x7b3a080aa000, 28672, PROT_READ) = 0 mprotect(0x7b3a06e73000, 28672, PROT_READ) = 0 mprotect(0x7b3a080f3000, 4096, PROT_READ) = 0 mprotect(0x7b3a071ed000, 45056, PROT_READ) = 0 mprotect(0x7b3a07910000, 2883584, PROT_READ) = 0 mprotect(0x7b3a07f15000, 90112, PROT_READ) = 0 mprotect(0x7b3a0813a000, 4096, PROT_READ) = 0 mprotect(0x7b3a081f9000, 12288, PROT_READ) = 0 mprotect(0x7b3a08b29000, 45056, PROT_READ) = 0 mprotect(0x7b3a08b9e000, 8192, PROT_READ) = 0 mprotect(0x7b3a08978000, 122880, PROT_READ) = 0 mprotect(0x7b3a08c54000, 8192, PROT_READ) = 0 mprotect(0x7b3a08d34000, 8192, PROT_READ) = 0 mprotect(0x7b3a096d0000, 4096, PROT_READ) = 0 mprotect(0x7b3a08d81000, 8192, PROT_READ) = 0 mprotect(0x7b3a08dd8000, 8192, PROT_READ) = 0 mprotect(0x7b3a08e72000, 16384, PROT_READ) = 0 mprotect(0x7b3a096f4000, 8192, PROT_READ) = 0 mprotect(0x7b3a08ff5000, 12288, PROT_READ) = 0 mprotect(0x7b3a09751000, 12288, PROT_READ) = 0 mprotect(0x7b3a09768000, 4096, PROT_READ) = 0 mprotect(0x7b3a09786000, 4096, PROT_READ) = 0 mprotect(0x7b3a0978c000, 4096, PROT_READ) = 0 mprotect(0x7b3a0968a000, 90112, PROT_READ) = 0 mprotect(0x7b3a09797000, 4096, PROT_READ) = 0 mprotect(0x7b3a097c8000, 8192, PROT_READ) = 0 mprotect(0x7b3a097d8000, 4096, PROT_READ) = 0 mprotect(0x7b3a09897000, 53248, PROT_READ) = 0 mprotect(0x7b3a0a489000, 4096, PROT_READ) = 0 mprotect(0x7b3a098da000, 4096, PROT_READ) = 0 mprotect(0x7b3a098f0000, 4096, PROT_READ) = 0 mprotect(0x7b3a09e40000, 4096, PROT_READ) = 0 mprotect(0x7b3a09936000, 4096, PROT_READ) = 0 mprotect(0x7b3a09a35000, 8192, PROT_READ) = 0 mprotect(0x7b3a09e55000, 4096, PROT_READ) = 0 mprotect(0x7b3a09bf4000, 24576, PROT_READ) = 0 mprotect(0x7b3a09e6b000, 4096, PROT_READ) = 0 mprotect(0x7b3a09ed1000, 8192, PROT_READ) = 0 mprotect(0x7b3a0a498000, 4096, PROT_READ) = 0 mprotect(0x7b3a09f01000, 4096, PROT_READ) = 0 mprotect(0x7b3a09f32000, 12288, PROT_READ) = 0 mprotect(0x7b3a09f87000, 8192, PROT_READ) = 0 mprotect(0x7b3a0a4a6000, 4096, PROT_READ) = 0 mprotect(0x7b3a0a4d1000, 4096, PROT_READ) = 0 mprotect(0x7b3a0a4da000, 4096, PROT_READ) = 0 mprotect(0x7b3a09ffb000, 12288, PROT_READ) = 0 mprotect(0x7b3a0a4fa000, 4096, PROT_READ) = 0 mprotect(0x7b3a0a51b000, 12288, PROT_READ) = 0 mprotect(0x7b3a0a556000, 4096, PROT_READ) = 0 mprotect(0x7b3a09e24000, 20480, PROT_READ) = 0 mprotect(0x7b3a0a458000, 61440, PROT_READ) = 0 mprotect(0x7b3a0a58a000, 8192, PROT_READ) = 0 mprotect(0x7b3a0a5be000, 4096, PROT_READ) = 0 mprotect(0x7b3a0a60b000, 12288, PROT_READ) = 0 mprotect(0x7b3a0a7b4000, 53248, PROT_READ) = 0 mprotect(0x7b3a0a7fb000, 8192, PROT_READ) = 0 mprotect(0x7b3a0a828000, 8192, PROT_READ) = 0 mprotect(0x7b3a0a835000, 4096, PROT_READ) = 0 mprotect(0x5abccc7db000, 8192, PROT_READ) = 0 mmap(NULL, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39f9b2b000 mprotect(0x7b3a0a873000, 8192, PROT_READ) = 0 prlimit64(0, RLIMIT_STACK, NULL, {rlim_cur=8192*1024, rlim_max=RLIM64_INFINITY}) = 0 munmap(0x7b39fae5d000, 131979) = 0 mmap(NULL, 327680, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39f1d0a000 mmap(NULL, 2097152, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e9400000 openat(AT_FDCWD, "/proc/meminfo", O_RDONLY) = 3 fstat(3, {st_mode=S_IFREG|0444, st_size=0, ...}) = 0 read(3, "MemTotal: 16146572 kB\nMemF"..., 1024) = 1024 read(3, " 74900 kB\nVmallocChunk: "..., 1024) = 563 close(3) = 0 munmap(0x7b39e9400000, 2097152) = 0 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39f0700000 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39eff00000 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39ef700000 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39eef00000 getuid() = 1000 geteuid() = 1000 getgid() = 1000 getegid() = 1000 openat(AT_FDCWD, "/sys/devices/system/cpu/possible", O_RDONLY|O_CLOEXEC) = 3 read(3, "0-15\n", 1024) = 5 close(3) = 0 sched_getaffinity(375096, 8, [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]) = 8 futex(0x7b39ee7fd61c, FUTEX_WAKE_PRIVATE, 2147483647) = 0 futex(0x7b39ee7fd628, FUTEX_WAKE_PRIVATE, 2147483647) = 0 rt_sigaction(SIGSEGV, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 rt_sigaction(SIGBUS, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 rt_sigaction(SIGILL, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 rt_sigaction(SIGFPE, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 sigaltstack({ss_sp=0x7b39f0719f00, ss_flags=0, ss_size=67584}, NULL) = 0 getcwd("/home/nirva", 1024) = 12 access("/home/nirva/quartus.ini", F_OK) = -1 ENOENT (No such file or directory) access("/home/nirva/quartus.ini", F_OK) = -1 ENOENT (No such file or directory) access("/home/nirva/.altera.quartus/quartus.ini", F_OK) = -1 ENOENT (No such file or directory) stat("/opt/intelFPGA/23.1/quartus/adm/quartus", 0x7ffec5849100) = -1 ENOENT (No such file or directory) stat("/opt/intelFPGA/23.1/quartus/linux64/quartus", {st_mode=S_IFREG|0755, st_size=25704, ...}) = 0 getcwd("/home/nirva", 1024) = 12 stat("/opt/intelFPGA/23.1/quartus/linux64/libccl_gen.so", {st_mode=S_IFREG|0755, st_size=533920, ...}) = 0 readlink("/opt", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) faccessat2(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/", F_OK, AT_EACCESS) = 0 readlink("/opt", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848220, 1023) = -1 EINVAL (Invalid argument) faccessat2(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/", F_OK, AT_EACCESS) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/quartus.ini", F_OK) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/bin/quartus.ini", F_OK) = -1 ENOENT (No such file or directory) access("", F_OK) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/proc/self/stat", O_RDONLY) = 3 fstat(3, {st_mode=S_IFREG|0444, st_size=0, ...}) = 0 lseek(3, 0, SEEK_SET) = 0 read(3, "375096 (quartus) R 375093 375093"..., 1024) = 332 close(3) = 0 openat(AT_FDCWD, "/etc/localtime", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=1430, ...}) = 0 fstat(3, {st_mode=S_IFREG|0644, st_size=1430, ...}) = 0 read(3, "TZif2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"..., 4096) = 1430 lseek(3, -901, SEEK_CUR) = 529 read(3, "TZif2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"..., 4096) = 901 close(3) = 0 ioctl(1, TCGETS, {c_iflag=ICRNL|IXON|IUTF8, c_oflag=NL0|CR0|TAB0|BS0|VT0|FF0|OPOST|ONLCR, c_cflag=B38400|CS8|CREAD, c_lflag=ISIG|ICANON|ECHO|ECHOE|ECHOK|IEXTEN|ECHOCTL|ECHOKE, ...}) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/common/devxml/cag/dynamic_atom_symbols.xml", O_RDONLY) = 3 read(3, "\254\357\1\0\0\0\0\0\227\335\22\371\234\250;PO\251\f\5\1\6\360*\262\236`\217k\244A\304"..., 8191) = 8191 read(3, "`c\2x\354\202\362f\345i\319\304\251\t\226@c\217\267\327L\243gC\357\3342\211\303\346m"..., 24585) = 24585 read(3, "~\266\2743\364\272\f\31\7\333\362\3\242\262\317\34\3269\312\276\244\37w\252\353c\324\310DU\26\376"..., 8191) = 8191 mmap(NULL, 3149824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e92ff000 read(3, ")\203\225\357\202\372<6i\255XV$\330\257\327s\244W\342b\247mo\350/\327~\303\1\266\213"..., 24577) = 24577 read(3, "n\252-ik\6A?\301\216\1\274\355\311\3242$\305\204\324\232\365\267\211C4l\203vC\356\305"..., 8191) = 8191 mmap(NULL, 3149824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e8ffe000 mmap(NULL, 3149824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e8cfd000 read(3, "\25\262\222M\2\7\177\317\304x\1\3\272\302r\27\\\275\0\0275\207\267.U\311I\363\263Z\2261"..., 24577) = 24577 read(3, "\373>\204\340\372\217\243Si\25\215\"h\3419\226\333\323\343\203\306o\3340\300w"..., 24577) = 24577 read(3, "\272^\254>\304\273\273\257{\34\2110\1\6\313\345\275\tu\17rnA.\354\273\23\364\207:x\276"..., 8191) = 7296 mmap(NULL, 3149824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e86fb000 mmap(NULL, 3149824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e83fa000 read(3, "", 25472) = 0 close(3) = 0 munmap(0x7b39e8cfd000, 3149824) = 0 munmap(0x7b39e8ffe000, 3149824) = 0 mmap(NULL, 3149824, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e8ffe000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e8cfe000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e80fa000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e7dfa000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e7afa000 openat(AT_FDCWD, "/sys/devices/system/cpu/online", O_RDONLY|O_CLOEXEC) = 3 read(3, "0-15\n", 1024) = 5 close(3) = 0 openat(AT_FDCWD, "/sys/devices/system/cpu/online", O_RDONLY|O_CLOEXEC) = 3 read(3, "0-15\n", 1024) = 5 close(3) = 0 openat(AT_FDCWD, "/sys/devices/system/cpu/online", O_RDONLY|O_CLOEXEC) = 3 read(3, "0-15\n", 1024) = 5 close(3) = 0 prlimit64(0, RLIMIT_STACK, NULL, {rlim_cur=8192*1024, rlim_max=RLIM64_INFINITY}) = 0 prlimit64(0, RLIMIT_STACK, {rlim_cur=10240*1024, rlim_max=RLIM64_INFINITY}, NULL) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/quartus.dep", O_RDONLY) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=2501, ...}) = 0 read(3, "sys_ictq\nsys_qgq\nmega_qsysipc\nsy"..., 4096) = 2501 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_ictq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_ictq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=302, ...}) = 0 read(4, "Qt5Core\nQt5Gui\nQt5Widgets\nQt5Net"..., 4096) = 302 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_qgq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_qgq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=300, ...}) = 0 read(4, "ccl_cfg_ini\nccl_ver\nccl_fio\nccl_"..., 4096) = 300 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_qsysipc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_qsysipc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=272, ...}) = 0 read(4, "Qt5Core\nccl_atcl\nccl_thr\nccl_cfg"..., 4096) = 272 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_qui.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_qui.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=566, ...}) = 0 read(4, "Qt5Core\nQt5Gui\nQt5Widgets\nQt5Net"..., 4096) = 566 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_pjc_tcl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_pjc_tcl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=450, ...}) = 0 read(4, "ccl_tst\nccl_ntf\nccl_atcl\nccl_cfg"..., 4096) = 450 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libprj_asl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/prj_asl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=398, ...}) = 0 read(4, "prj_asl_dc\nace_adb\ndb_hdb\ndb_fin"..., 4096) = 398 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_fin.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_fin.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=396, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 396 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libace_adb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ace_adb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=791, ...}) = 0 read(4, "ace_acest\natm_astr\natm_autil\natm"..., 4096) = 791 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_rpt.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_rpt.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=736, ...}) = 0 read(4, "atm_astr\natm_autil\natm_cga\nccl_b"..., 4096) = 736 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/liblegality_lregion.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/legality_lregion.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=298, ...}) = 0 read(4, "atm_cga\nccl_cfg_ini\nccl_gen\nccl_"..., 4096) = 298 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libace_acest.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ace_acest.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=214, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_fio\nccl_msg\n"..., 4096) = 214 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libprj_asl_dc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/prj_asl_dc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=322, ...}) = 0 read(4, "atm_cga\natm_astr\ndb_hdb\nddb_dev\n"..., 4096) = 322 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_flow.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_flow.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=444, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_tst\nccl_gen\n"..., 4096) = 444 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_hcu.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_hcu.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=201, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_gen\nccl_fio\n"..., 4096) = 201 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_rcomp.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_rcomp.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=217, ...}) = 0 read(4, "ccl_mem\nccl_fio\nccl_gen\nccl_msg\n"..., 4096) = 217 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_py.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_py.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=233, ...}) = 0 read(4, "ccl_atcl\nccl_curl\nccl_fio\nccl_cf"..., 4096) = 233 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_ice.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_ice.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=391, ...}) = 0 read(4, "ccl_tst\nccl_mem\nccl_mio\nccl_big\n"..., 4096) = 391 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_sli.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_sli.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=283, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_cfg_ini\nccl_"..., 4096) = 283 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_chi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_chi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=265, ...}) = 0 read(4, "ccl_tst\nccl_mem\nccl_mio\nccl_big\n"..., 4096) = 265 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_hapi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_hapi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=165, ...}) = 0 read(4, "jtag_client\nccl_thr\nboost_regex-"..., 4096) = 165 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libjtag_client.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/jtag_client.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libsld_atcio.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_atcio.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=178, ...}) = 0 read(4, "ccl_mem\nccl_msg\nsld_sdr\nddb_dstr"..., 4096) = 178 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_sdr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_sdr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=238, ...}) = 0 read(4, "sld_sad\nccl_tst\nccl_zlib\nccl_mem"..., 4096) = 238 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsaui_eui.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/saui_eui.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=220, ...}) = 0 read(4, "ccl_big\ndb_acf\nccl_fio\nccl_gen\nc"..., 4096) = 220 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_wizmancmd_sh.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_wizmancmd_sh.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=354, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_gen\nddb_dstr"..., 4096) = 354 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_rules_validator.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_rules_validator.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=202, ...}) = 0 read(4, "mega_info\nmega_stl\nmega_regexp\nc"..., 4096) = 202 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmlib_int.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mlib_int.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_regexp.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_regexp.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_info.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_info.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=179, ...}) = 0 read(4, "mega_xml_parser\nmega_stl\ncbx_uti"..., 4096) = 179 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_xml_parser.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_xml_parser.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=154, ...}) = 0 read(4, "mega_stl\nboost_regex-x64\nboost_s"..., 4096) = 154 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libedt_gio.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/edt_gio.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=246, ...}) = 0 read(4, "ccl_msg\nccl_mem\nccl_cfg_ini\nccl_"..., 4096) = 246 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsynth_sio.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/synth_sio.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=244, ...}) = 0 read(4, "ccl_msg\nccl_mem\nccl_cfg_ini\nccl_"..., 4096) = 244 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libgcl_gtoq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/gcl_gtoq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=187, ...}) = 0 read(4, "gcl_afcq\ngcl_cglq\nccl_gen\nccl_me"..., 4096) = 187 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libgcl_cglq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/gcl_cglq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=161, ...}) = 0 read(4, "ccl_mem\nccl_msg\nboost_regex-x64\n"..., 4096) = 161 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libgcl_afcq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/gcl_afcq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=348, ...}) = 0 read(4, "Qt5Core\nQt5Gui\nQt5Widgets\nQt5Svg"..., 4096) = 348 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libgcl_afcq_tb2.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/gcl_afcq_tb2.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=197, ...}) = 0 read(4, "ccl_thr\nccl_mem\nccl_gen\nccl_msg\n"..., 4096) = 197 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libgcl_cfgq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/gcl_cfgq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=205, ...}) = 0 read(4, "Qt5Core\nccl_cfg_ini\nccl_fio\nccl_"..., 4096) = 205 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_tinyxml2.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_tinyxml2.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=161, ...}) = 0 read(4, "ccl_gen\nccl_mem\nboost_regex-x64\n"..., 4096) = 161 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Svg.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Svg.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libdb_qtk.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_qtk.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=736, ...}) = 0 read(4, "db_acf\natm_astr\ndb_cdb\ndb_cdb_re"..., 4096) = 736 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsynth_sgn_qic_dpi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/synth_sgn_qic_dpi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=228, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_gen\nccl_fio\n"..., 4096) = 228 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_sci.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_sci.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=320, ...}) = 0 read(4, "ccl_tst\nccl_mem\nsys_cpt\nsys_flow"..., 4096) = 320 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsld_sad.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sld_sad.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=213, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_fio\nccl_cfg_"..., 4096) = 213 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_ipqx.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_ipqx.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=262, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_thr\nccl_ipc\n"..., 4096) = 262 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtpi_miu.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tpi_miu.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=284, ...}) = 0 read(4, "db_cdb_mgr\nddb_dev\ntpi_tset\nccl_"..., 4096) = 284 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_llu.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_llu.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=383, ...}) = 0 read(4, "db_acf\ndb_cdb\ndb_dbmui\ndb_hdb\ndb"..., 4096) = 383 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_tdc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_tdc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=460, ...}) = 0 read(4, "ccl_msg\nccl_mem\nccl_fio\nccl_gen\n"..., 4096) = 460 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_sta.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_sta.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=693, ...}) = 0 read(4, "atm_cga\nccl_atcl\nccl_big\nccl_cfg"..., 4096) = 693 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_ddrtcl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_ddrtcl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=386, ...}) = 0 read(4, "ccl_fio\nccl_gen\nccl_mem\nccl_msg\n"..., 4096) = 386 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_a2t.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_a2t.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=611, ...}) = 0 read(4, "ccl_msg\nccl_mem\nccl_gen\nccl_qtl\n"..., 4096) = 611 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dygr_fdi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dygr_fdi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=291, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 291 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_tapi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_tapi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=486, ...}) = 0 read(4, "ccl_mem\nccl_tst\nccl_qtl\nccl_qsym"..., 4096) = 486 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_tis.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_tis.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=662, ...}) = 0 read(4, "ccl_mem\ndb_cdb\ndb_cdb_re\ndb_cdb_"..., 4096) = 662 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_b2t.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_b2t.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=465, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_fio\nccl_gen\n"..., 4096) = 465 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dlib.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dlib.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=272, ...}) = 0 read(4, "ccl_mem\ndb_pdb\nccl_msg\nccl_qtl\nc"..., 4096) = 272 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_tim_rc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_tim_rc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=239, ...}) = 0 read(4, "tsm_nlspc\nccl_msg\nccl_mem\nddb_dy"..., 4096) = 239 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_pti.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_pti.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=637, ...}) = 0 read(4, "atm_astr\natm_cga\nccl_big\nccl_cfg"..., 4096) = 637 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_fdi_data.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_fdi_data.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=469, ...}) = 0 read(4, "ccl_tst\nccl_cfg_ini\nccl_fio\nccl_"..., 4096) = 469 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_dist.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_dist.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=231, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_mps\nccl_rpc\n"..., 4096) = 231 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_ipsta.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_ipsta.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=283, ...}) = 0 read(4, "ccl_gen\nccl_mem\nccl_msg\nccl_qtl\n"..., 4096) = 283 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dspf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dspf.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=343, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_qtl\nccl_fio\n"..., 4096) = 343 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libqcl_clk.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/qcl_clk.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=464, ...}) = 0 read(4, "ccl_atcl\nccl_cfg_ini\nccl_err\nccl"..., 4096) = 464 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dcalc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dcalc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=282, ...}) = 0 read(4, "atm_astr\nccl_atcl\nccl_cfg_ini\ncc"..., 4096) = 282 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_qspc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_qspc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=258, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 258 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_rpc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_rpc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=205, ...}) = 0 read(4, "Qt5Core\nccl_mem\nccl_msg\nccl_thr\n"..., 4096) = 205 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_mps.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_mps.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=189, ...}) = 0 read(4, "Qt5Core\nccl_mem\nccl_msg\nccl_thr\n"..., 4096) = 189 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_tim.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_tim.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=406, ...}) = 0 read(4, "ccl_mem\ndb_cdb\ndb_cdb_re\ndb_cdb_"..., 4096) = 406 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_sin.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_sin.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=405, ...}) = 0 read(4, "atm_astr\natm_cga\nccl_atcl\nccl_cf"..., 4096) = 405 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_ioo.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_ioo.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=407, ...}) = 0 read(4, "atm_astr\natm_cga\nccl_atcl\nccl_bi"..., 4096) = 407 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_nlspc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_nlspc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=268, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 268 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_superlu.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_superlu.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=170, ...}) = 0 read(4, "tsm_blas\nccl_mem\nccl_msg\nboost_r"..., 4096) = 170 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_blas.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_blas.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_metis.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_metis.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_core.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b2_core.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=558, ...}) = 0 read(4, "atm_astr\natm_cga\natm_autil\nccl_a"..., 4096) = 558 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libpgm_options.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/pgm_options.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=170, ...}) = 0 read(4, "ccl_mem\nccl_msg\nprotobuf\nboost_r"..., 4096) = 170 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libqcl_iopt.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/qcl_iopt.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=293, ...}) = 0 read(4, "ccl_cfg_ini\nccl_err\nccl_gen\nccl_"..., 4096) = 293 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_routing.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b2_routing.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=413, ...}) = 0 read(4, "atm_cga\nccl_atcl\nccl_big\nccl_cfg"..., 4096) = 413 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_shm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_shm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=221, ...}) = 0 read(4, "Qt5Core\nccl_mem\nccl_msg\nccl_thr\n"..., 4096) = 221 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_cdb_tcl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b2_cdb_tcl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=534, ...}) = 0 read(4, "atm_astr\natm_autil\natm_cga\nccl_a"..., 4096) = 534 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_qcu.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_qcu.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=594, ...}) = 0 read(4, "ccl_thr\nccl_tst\nccl_mem\nccl_msg\n"..., 4096) = 594 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtpi_tset.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tpi_tset.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=234, ...}) = 0 read(4, "db_acf\ndb_hdb\ndb_wys\nddb_dev\nccl"..., 4096) = 234 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtpi_eti.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tpi_eti.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=237, ...}) = 0 read(4, "ccl_msg\nccl_fio\nccl_mem\nsys_cpt\n"..., 4096) = 237 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_pjc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_pjc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=354, ...}) = 0 read(4, "ccl_tst\nccl_ntf\nccl_atcl\nccl_bat"..., 4096) = 354 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_proj.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_proj.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=322, ...}) = 0 read(4, "db_acf\nccl_atcl\ncomp_qhd\ndb_dbm\n"..., 4096) = 322 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_cpt_hdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_cpt_hdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=192, ...}) = 0 read(4, "sys_cpt\ndb_hdb\nccl_fio\nccl_qtl\nc"..., 4096) = 192 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libtsm_tdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/tsm_tdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=479, ...}) = 0 read(4, "ccl_msg\nccl_mem\nccl_atcl\nccl_big"..., 4096) = 479 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_vdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_vdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=234, ...}) = 0 read(4, "db_acf\nccl_qtl\nccl_big\nccl_mem\nc"..., 4096) = 234 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_qhd_dbmui.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_qhd_dbmui.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=202, ...}) = 0 read(4, "ccl_mem\nccl_msg\ncomp_qhd\ndb_acf\n"..., 4096) = 202 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_qhd.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_qhd.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=568, ...}) = 0 read(4, "Qt5Core\natm_atmx\natm_cga\nccl_atc"..., 4096) = 568 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libperiph_fpp.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/periph_fpp.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=227, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 227 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_rcf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_rcf.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=376, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_fio\nccl_cfg"..., 4096) = 376 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_lampas.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_lampas.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=325, ...}) = 0 read(4, "ccl_mem\ndb_dbs\ndb_constra\ndb_are"..., 4096) = 325 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_ares.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_ares.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=362, ...}) = 0 read(4, "atm_astr\natm_cga\nccl_atcl\nccl_bi"..., 4096) = 362 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_rapid.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_rapid.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=532, ...}) = 0 read(4, "atm_cga\nccl_mem\nccl_msg\nccl_put\n"..., 4096) = 532 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_cdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b2_cdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=612, ...}) = 0 read(4, "atm_astr\natm_autil\natm_cga\nccl_a"..., 4096) = 612 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b2_cfg.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b2_cfg.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=290, ...}) = 0 read(4, "ccl_cfg_ini\nccl_qsym\nccl_fio\nccl"..., 4096) = 290 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_idb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_idb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=241, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 241 read(4, "", 4096) = 0 close(4) = 0 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e77fa000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e74fa000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e71fa000 mmap(NULL, 3145728, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7b39e6efa000 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_qtl_string_match.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_qtl_string_match.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=198, ...}) = 0 read(4, "ccl_mem\nccl_err\nccl_atcl\nccl_fio"..., 4096) = 198 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_mpp.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_mpp.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=368, ...}) = 0 read(4, "ccl_mem\nccl_tst\nccl_qtl\nccl_qsym"..., 4096) = 368 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_logdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_logdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=212, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_msg\nccl_thr\n"..., 4096) = 212 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_rutil.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_rutil.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=274, ...}) = 0 read(4, "ddb_dmgr\nddb_dev\nddb_dstr\nccl_me"..., 4096) = 274 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libatm_atmx.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/atm_atmx.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=462, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_gen\nccl_fio\n"..., 4096) = 462 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=511, ...}) = 0 read(4, "atm_astr\natm_autil\natm_cga\nccl_a"..., 4096) = 511 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_tinfo.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_tinfo.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=236, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_gen\nccl_qtl\n"..., 4096) = 236 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_b2b.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_b2b.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=210, ...}) = 0 read(4, "ccl_mem\nccl_thr\nccl_gen\nccl_msg\n"..., 4096) = 210 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cut.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cut.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=1005, ...}) = 0 read(4, "qcl_pllc\ndb_acf\ndb_cal\ndb_cal_ge"..., 4096) = 1005 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_qcu_tb2.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_qcu_tb2.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=204, ...}) = 0 read(4, "ccl_thr\nccl_mem\nccl_gen\nccl_msg\n"..., 4096) = 204 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsynth_bdd.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/synth_bdd.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=181, ...}) = 0 read(4, "ccl_cfg_ini\nccl_msg\nccl_gen\nccl_"..., 4096) = 181 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcbx_util.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/cbx_util.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=164, ...}) = 0 read(4, "mega_stl\nmega_mfam\nboost_regex-x"..., 4096) = 164 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_mfam.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_mfam.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libmega_stl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/mega_stl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libqcl_pll.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/qcl_pll.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=289, ...}) = 0 read(4, "ccl_atcl\nccl_qtl\nccl_mem\nccl_msg"..., 4096) = 289 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_itcl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_itcl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=169, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_msg\nboost_re"..., 4096) = 169 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_hinf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_hinf.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=211, ...}) = 0 read(4, "ccl_gen\nccl_mem\nccl_msg\nccl_qsym"..., 4096) = 211 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_rbc_util.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_rbc_util.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=212, ...}) = 0 read(4, "ccl_big\nccl_mem\nccl_msg\nccl_qsym"..., 4096) = 212 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_constra.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_constra.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=281, ...}) = 0 read(4, "ccl_mem\nccl_fio\nccl_msg\nccl_gen\n"..., 4096) = 281 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=442, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 442 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_emif.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_av_emif.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_lvds.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_av_lvds.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_nf_hssi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_nf_hssi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_hssi.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_av_hssi.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_cv_pll.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_cv_pll.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_av_pll.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_av_pll.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_generic.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_generic.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=340, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 340 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cal_util.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cal_util.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=311, ...}) = 0 read(4, "atm_cga\natm_astr\nccl_big\nccl_cfg"..., 4096) = 311 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_mgr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_mgr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=392, ...}) = 0 read(4, "atm_autil\natm_cga\nccl_atcl\nccl_c"..., 4096) = 392 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_ibr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_ibr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=246, ...}) = 0 read(4, "ccl_qsym\nccl_gen\nccl_mem\nccl_thr"..., 4096) = 246 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b_bcm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b_bcm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=335, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_fio\nccl_gen\n"..., 4096) = 335 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_u2b_cfg.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_u2b_cfg.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=297, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_fio\nccl_gen\n"..., 4096) = 297 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_re.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_re.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=344, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 344 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_a2c.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_a2c.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=312, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 312 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_msf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_msf.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=236, ...}) = 0 read(4, "ccl_mem\nccl_err\nccl_msg\nccl_cfg_"..., 4096) = 236 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cut_dev.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cut_dev.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=333, ...}) = 0 read(4, "ccl_atcl\nccl_mem\nccl_msg\nccl_gen"..., 4096) = 333 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dbcm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dbcm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=303, ...}) = 0 read(4, "ccl_atcl\nccl_fio\nccl_gen\nccl_mem"..., 4096) = 303 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_ihc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_ihc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=221, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 221 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dygr_qdl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dygr_qdl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=241, ...}) = 0 read(4, "ccl_cfg_ini\nccl_msg\nccl_gen\nccl_"..., 4096) = 241 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libprotobuf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/protobuf.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libatm_cga.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/atm_cga.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=317, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_fio\nccl_msg\n"..., 4096) = 317 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_factory.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_factory.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=525, ...}) = 0 read(4, "ccl_cfg_ini\nccl_msg\nccl_mem\nccl_"..., 4096) = 525 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_syn.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_syn.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=358, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 358 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_cyclonev.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_cyclonev.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_arriav.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_arriav.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=358, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 358 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_nadder.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_nadder.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=358, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 358 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_nightfury.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_nightfury.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=358, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 358 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_dynamic.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_dynamic.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=381, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 381 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_stratixv.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_stratixv.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=381, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 381 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_fusion.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_fusion.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_cuda.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_cuda.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_titan.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_titan.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_tgx.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_tgx.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_stingray.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_stingray.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_hcx.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_hcx.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_generic.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_generic.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=247, ...}) = 0 read(4, "ccl_gen\nccl_mem\nccl_msg\nccl_fio\n"..., 4096) = 247 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_arm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_arm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_ygr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_ygr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=350, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 350 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=414, ...}) = 0 read(4, "atm_astr\natm_autil\nccl_big\nccl_f"..., 4096) = 414 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dloc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dloc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=216, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_gen\nccl_cfg_"..., 4096) = 216 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_db.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_db.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=224, ...}) = 0 read(4, "ccl_fio\nccl_qtl\nccl_msg\nccl_mem\n"..., 4096) = 224 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_sgate.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_sgate.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=415, ...}) = 0 read(4, "db_cdb\nccl_tst\nqcl_pllc\nccl_qtl\n"..., 4096) = 415 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_idu.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_idu.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=315, ...}) = 0 read(4, "db_acf\ndb_dbmui\ndb_hdb\ndb_dbm\ndb"..., 4096) = 315 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_rdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_rdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=325, ...}) = 0 read(4, "ccl_atcl\nccl_big\nccl_cfg_ini\nccl"..., 4096) = 325 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_rstr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_rstr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=186, ...}) = 0 read(4, "ccl_gen\nccl_mem\nccl_msg\nccl_atcl"..., 4096) = 186 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_dbmui.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_dbmui.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=238, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_fstr\nccl"..., 4096) = 238 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_flow_util.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_flow_util.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=238, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_qtl\nccl_fio\n"..., 4096) = 238 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_kpt.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_kpt.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=221, ...}) = 0 read(4, "ccl_cfg_ini\ndb_hdb\nccl_mem\nccl_m"..., 4096) = 221 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dmgr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dmgr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=275, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 275 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dpow.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dpow.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=237, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 237 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dtm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dtm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=212, ...}) = 0 read(4, "ccl_fio\nccl_gen\nccl_mem\nccl_msg\n"..., 4096) = 212 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dygr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dygr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=270, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 270 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dmig.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dmig.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=224, ...}) = 0 read(4, "ccl_cfg_ini\nccl_gen\nccl_msg\nccl_"..., 4096) = 224 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dev.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dev.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=323, ...}) = 0 read(4, "ccl_cfg_ini\nccl_tst\nccl_big\nccl_"..., 4096) = 323 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_wys.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_wys.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=278, ...}) = 0 read(4, "ccl_mem\nccl_qsym\nccl_msg\nccl_thr"..., 4096) = 278 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb_atom_definition.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb_atom_definition.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=267, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_err\nccl_thr\n"..., 4096) = 267 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_put.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_put.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=185, ...}) = 0 read(4, "ccl_thr\nccl_gen\nccl_mem\nccl_msg\n"..., 4096) = 185 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libqcl_pllc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/qcl_pllc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=230, ...}) = 0 read(4, "ccl_mem\nccl_qtl\nccl_msg\nccl_fio\n"..., 4096) = 230 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_cdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_cdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=267, ...}) = 0 read(4, "ccl_mem\nccl_big\nccl_cfg_ini\nccl_"..., 4096) = 267 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_hut.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_hut.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=217, ...}) = 0 read(4, "ccl_mem\nccl_msg\nccl_fio\nccl_gen\n"..., 4096) = 217 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_mio.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_mio.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=243, ...}) = 0 read(4, "ccl_msg\nccl_mem\nccl_gen\nccl_fio\n"..., 4096) = 243 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_hdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_hdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=292, ...}) = 0 read(4, "ccl_atcl\nccl_big\nccl_cfg_ini\nccl"..., 4096) = 292 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_qdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_qdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=259, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_qtl\nccl_msg\n"..., 4096) = 259 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_afm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_afm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=214, ...}) = 0 read(4, "ccl_cfg_ini\nccl_atcl\nccl_qtl\nccl"..., 4096) = 214 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_dbm.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_dbm.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=205, ...}) = 0 read(4, "ccl_gen\nccl_fio\nccl_mem\nccl_msg\n"..., 4096) = 205 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_cksum.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_cksum.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=177, ...}) = 0 read(4, "ccl_mem\nccl_fio\nccl_gen\nccl_msg\n"..., 4096) = 177 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_qcu_facade.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_qcu_facade.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=153, ...}) = 0 read(4, "ccl_mem\nboost_regex-x64\nboost_se"..., 4096) = 153 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libatm_autil.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/atm_autil.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=176, ...}) = 0 read(4, "ccl_mem\nccl_qtl\nccl_msg\ndb_pdb\nb"..., 4096) = 176 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libatm_astr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/atm_astr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=221, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_fio\nccl_msg\n"..., 4096) = 221 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_dyn.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_dyn.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=216, ...}) = 0 read(4, "ccl_qtl\nccl_err\nccl_xml\nccl_fio\n"..., 4096) = 216 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libcomp_qexe.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/comp_qexe.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=264, ...}) = 0 read(4, "ccl_fstr\nccl_tst\nccl_mem\nccl_msg"..., 4096) = 264 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_cloud.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_cloud.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=245, ...}) = 0 read(4, "ccl_msg\nccl_bat\nccl_curl\nccl_gen"..., 4096) = 245 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_curl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_curl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=230, ...}) = 0 read(4, "ccl_gen\nccl_msg\nccl_qtl\nccl_thr\n"..., 4096) = 230 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_tb2.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_tb2.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=153, ...}) = 0 read(4, "ccl_mem\nboost_regex-x64\nboost_se"..., 4096) = 153 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_acf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_acf.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=272, ...}) = 0 read(4, "ccl_atcl\nccl_qtl\nccl_tst\nccl_fio"..., 4096) = 272 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libddb_dstr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ddb_dstr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=204, ...}) = 0 read(4, "ccl_mem\nccl_thr\nccl_msg\nccl_gen\n"..., 4096) = 204 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_dbs.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_dbs.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=206, ...}) = 0 read(4, "ccl_mem\nccl_thr\nccl_msg\nccl_qsym"..., 4096) = 206 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_qsym.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_qsym.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=212, ...}) = 0 read(4, "ccl_cfg_ini\nccl_qtl\nccl_err\nccl_"..., 4096) = 212 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libsys_cpt.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/sys_cpt.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=222, ...}) = 0 read(4, "ccl_tst\nccl_fio\nccl_cfg_ini\nccl_"..., 4096) = 222 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_ntfq.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_ntfq.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=181, ...}) = 0 read(4, "ccl_thr\nccl_mem\nccl_cfg_ini\nccl_"..., 4096) = 181 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_ipc.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_ipc.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=206, ...}) = 0 read(4, "ccl_msg\nccl_atcl\nccl_cfg_ini\nccl"..., 4096) = 206 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_bat.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_bat.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=194, ...}) = 0 read(4, "ccl_atcl\nccl_gen\nccl_mem\nccl_qtl"..., 4096) = 194 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_ntf.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_ntf.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=169, ...}) = 0 read(4, "ccl_thr\nccl_mem\nccl_msg\nboost_re"..., 4096) = 169 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_msg.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_msg.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=288, ...}) = 0 read(4, "ccl_atcl\nccl_big\nccl_cfg_ini\nccl"..., 4096) = 288 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_xml.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_xml.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=198, ...}) = 0 read(4, "ccl_cfg_ini\nccl_fio\nccl_gen\nccl_"..., 4096) = 198 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libxerces-c.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/xerces-c.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libccl_sqlite3.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_sqlite3.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_interface.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_interface.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_big.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_big.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=196, ...}) = 0 read(4, "ccl_gen\nccl_mem\nccl_err\nccl_qtl\n"..., 4096) = 196 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libdb_pdb.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/db_pdb.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=229, ...}) = 0 read(4, "ccl_qtl\nccl_thr\nccl_err\nccl_mem\n"..., 4096) = 229 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_tst.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_tst.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=186, ...}) = 0 read(4, "ccl_atcl\nccl_gen\nccl_mem\nccl_thr"..., 4096) = 186 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_clw.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_clw.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=170, ...}) = 0 read(4, "ccl_zlib\nccl_err\nccl_mem\nboost_r"..., 4096) = 170 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_atcl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_atcl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=231, ...}) = 0 read(4, "ccl_thr\nccl_gen\nccl_qtl\nccl_fstr"..., 4096) = 231 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_fstr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_fstr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=185, ...}) = 0 read(4, "ccl_fio\nccl_gen\nccl_mem\nccl_qtl\n"..., 4096) = 185 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_qtl.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_qtl.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=190, ...}) = 0 read(4, "ccl_mem\nccl_gen\nccl_zlib\nccl_err"..., 4096) = 190 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_cfg_ini.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_cfg_ini.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=193, ...}) = 0 read(4, "ccl_mem\nccl_fio\nccl_gen\nccl_ver\n"..., 4096) = 193 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_zlib.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_zlib.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=153, ...}) = 0 read(4, "ccl_mem\nboost_regex-x64\nboost_se"..., 4096) = 153 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_gen.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_gen.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=185, ...}) = 0 read(4, "ccl_mem\nccl_fio\nccl_thr\nccl_ver\n"..., 4096) = 185 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_fio.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_fio.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=161, ...}) = 0 read(4, "ccl_mem\nccl_err\nboost_regex-x64\n"..., 4096) = 161 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_mem.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_mem.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=161, ...}) = 0 read(4, "ccl_err\nccl_thr\nboost_regex-x64\n"..., 4096) = 161 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_err.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_err.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=150, ...}) = 0 read(4, "ccl_thr\nccl_ver\nboost_regex-x64\n"..., 4096) = 150 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_ver.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_ver.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libccl_thr.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/ccl_thr.dep", O_RDONLY) = 4 fstat(4, {st_mode=S_IFREG|0644, st_size=145, ...}) = 0 read(4, "boost_regex-x64\nboost_serializat"..., 4096) = 145 read(4, "", 4096) = 0 close(4) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Test.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Test.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Qml.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Qml.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Network.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Network.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Widgets.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Widgets.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Gui.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Gui.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libQt5Core.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/Qt5Core.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libboost_regex-x64.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/boost_regex-x64.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libboost_serialization-x64.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/boost_serialization-x64.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libboost_filesystem-x64.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/boost_filesystem-x64.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libboost_system-x64.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/boost_system-x64.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libboost_program_options-x64.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/boost_program_options-x64.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libboost_unit_test_framework-x64.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/boost_unit_test_framework-x64.dep", O_RDONLY) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/libSafeString.so", F_OK) = 0 getcwd("/home/nirva", 1025) = 12 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/SafeString.dep", O_RDONLY) = -1 ENOENT (No such file or directory) read(3, "", 4096) = 0 close(3) = 0 access("/opt/intelFPGA/23.1/quartus/linux64//quartus_patch_log.txt", F_OK) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64//qvweid.fil", F_OK) = 0 access("/etc/SuSE-release", F_OK) = -1 ENOENT (No such file or directory) access("/etc/fedora-release", F_OK) = -1 ENOENT (No such file or directory) access("/etc/redhat-release", F_OK) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/etc/issue", O_RDONLY) = 3 read(3, "\\S{PRETTY_NAME} \\r (\\l)\n\n", 8191) = 25 close(3) = 0 openat(AT_FDCWD, "/etc/issue", O_RDONLY) = 3 read(3, "\\S{PRETTY_NAME} \\r (\\l)\n\n", 8191) = 25 close(3) = 0 openat(AT_FDCWD, "/proc/self/stat", O_RDONLY) = 3 fstat(3, {st_mode=S_IFREG|0444, st_size=0, ...}) = 0 lseek(3, 0, SEEK_SET) = 0 read(3, "375096 (quartus) R 375093 375093"..., 1024) = 332 close(3) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 access("/home/nirva/.altera.quartus", F_OK) = 0 access("/home/nirva/.altera.quartus/quartus2.ini", F_OK) = -1 ENOENT (No such file or directory) rt_sigaction(SIGSEGV, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 rt_sigaction(SIGBUS, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 rt_sigaction(SIGILL, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 rt_sigaction(SIGFPE, {sa_handler=0x7b39fa4c920e, sa_mask=[], sa_flags=SA_RESTORER|SA_NODEFER|SA_RESETHAND|SA_SIGINFO|0xffffffff00000000, sa_restorer=0x7b39ee24c1d0}, NULL, 8) = 0 openat(AT_FDCWD, "/proc/self/stat", O_RDONLY) = 3 fstat(3, {st_mode=S_IFREG|0444, st_size=0, ...}) = 0 lseek(3, 0, SEEK_SET) = 0 read(3, "375096 (quartus) R 375093 375093"..., 1024) = 332 close(3) = 0 futex(0x7b39ef6b13c8, FUTEX_WAKE_PRIVATE, 2147483647) = 0 geteuid() = 1000 getuid() = 1000 openat(AT_FDCWD, "/usr/lib/locale/locale-archive", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=3060144, ...}) = 0 mmap(NULL, 3060144, PROT_READ, MAP_PRIVATE, 3, 0) = 0x7b39e6c00000 close(3) = 0 getpid() = 375096 access("/proc/375096/exe", F_OK) = 0 lstat("/proc/375096/exe", {st_mode=S_IFLNK|0777, st_size=0, ...}) = 0 readlink("/proc", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/proc/375096", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/proc/375096/exe", "/opt/intelFPGA/23.1/quartus/linu"..., 1023) = 43 readlink("/opt", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/quartus", 0x7ffec58488a0, 1023) = -1 EINVAL (Invalid argument) access("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", F_OK) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", F_OK) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/qt.conf", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0444, st_size=22, ...}) = 0 fstat(3, {st_mode=S_IFREG|0444, st_size=22, ...}) = 0 fstat(3, {st_mode=S_IFREG|0444, st_size=22, ...}) = 0 read(3, "[Paths]\nPrefix = ./qt\n", 16384) = 22 read(3, "", 16362) = 0 stat("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", {st_mode=S_IFREG|0444, st_size=22, ...}) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 close(3) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/qt/plugins", F_OK) = 0 readlink("/opt", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/qt", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/qt/plugins", 0x7ffec5848bc0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt", 0x7ffec5848b80, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848b80, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848b80, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848b80, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848b80, 1023) = -1 EINVAL (Invalid argument) access("/opt/intelFPGA/23.1/quartus/linux64", F_OK) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/qt/plugins/platforms/.", F_OK) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/platforms/.", F_OK) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms", O_RDONLY|O_NONBLOCK|O_CLOEXEC|O_DIRECTORY) = 3 fstat(3, {st_mode=S_IFDIR|S_ISGID|0755, st_size=4096, ...}) = 0 getdents64(3, 0x7b39e70449f0 /* 7 entries */, 32768) = 232 getdents64(3, 0x7b39e70449f0 /* 0 entries */, 32768) = 0 close(3) = 0 readlink("/opt", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqlinuxfb.so", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqlinuxfb.so", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0555, st_size=608720, ...}) = 0 fstat(3, {st_mode=S_IFREG|0555, st_size=608720, ...}) = 0 mmap(NULL, 608720, PROT_READ, MAP_SHARED, 3, 0) = 0x7b39f0ccc000 close(3) = 0 munmap(0x7b39f0ccc000, 608720) = 0 readlink("/opt", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqminimal.so", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqminimal.so", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0555, st_size=197352, ...}) = 0 fstat(3, {st_mode=S_IFREG|0555, st_size=197352, ...}) = 0 mmap(NULL, 197352, PROT_READ, MAP_SHARED, 3, 0) = 0x7b39f3b63000 close(3) = 0 munmap(0x7b39f3b63000, 197352) = 0 readlink("/opt", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqoffscreen.so", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqoffscreen.so", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0555, st_size=237040, ...}) = 0 fstat(3, {st_mode=S_IFREG|0555, st_size=237040, ...}) = 0 mmap(NULL, 237040, PROT_READ, MAP_SHARED, 3, 0) = 0x7b39f1cd0000 close(3) = 0 munmap(0x7b39f1cd0000, 237040) = 0 readlink("/opt", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqvnc.so", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqvnc.so", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0555, st_size=370096, ...}) = 0 fstat(3, {st_mode=S_IFREG|0555, st_size=370096, ...}) = 0 mmap(NULL, 370096, PROT_READ, MAP_SHARED, 3, 0) = 0x7b39f17a5000 close(3) = 0 munmap(0x7b39f17a5000, 370096) = 0 readlink("/opt", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) readlink("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqxcb.so", 0x7ffec5848bd0, 1023) = -1 EINVAL (Invalid argument) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqxcb.so", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0555, st_size=23584, ...}) = 0 fstat(3, {st_mode=S_IFREG|0555, st_size=23584, ...}) = 0 mmap(NULL, 23584, PROT_READ, MAP_SHARED, 3, 0) = 0x7b39fae78000 close(3) = 0 munmap(0x7b39fae78000, 23584) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", F_OK) = 0 stat("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", {st_mode=S_IFREG|0444, st_size=22, ...}) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/qt/qtlogging.ini", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) stat("/home/nirva/.config/QtProject/qtlogging.ini", 0x7ffec58490f0) = -1 ENOENT (No such file or directory) stat("/home/nirva/.config/kdedefaults/QtProject/qtlogging.ini", 0x7ffec58490f0) = -1 ENOENT (No such file or directory) stat("/etc/xdg/QtProject/qtlogging.ini", 0x7ffec58490f0) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", F_OK) = 0 stat("/opt/intelFPGA/23.1/quartus/linux64/qt.conf", {st_mode=S_IFREG|0444, st_size=22, ...}) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 newfstatat(AT_FDCWD, "/etc/localtime", {st_mode=S_IFREG|0644, st_size=1430, ...}, 0) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqxcb.so.avx2", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) access("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqxcb.so.avx2", F_OK) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/libqxcb.so", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@!\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=23584, ...}) = 0 mmap(NULL, 20544, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fae78000 mmap(0x7b39fae7a000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fae7a000 mmap(0x7b39fae7b000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39fae7b000 mmap(0x7b39fae7c000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39fae7c000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5XcbQpa.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\3\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0K\3\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=1607656, ...}) = 0 mmap(NULL, 1288232, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39edec5000 mprotect(0x7b39edef5000, 1056768, PROT_NONE) = 0 mmap(0x7b39edef5000, 700416, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x30000) = 0x7b39edef5000 mmap(0x7b39edfa0000, 352256, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xdb000) = 0x7b39edfa0000 mmap(0x7b39edff7000, 32768, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x131000) = 0x7b39edff7000 mmap(0x7b39edfff000, 2088, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39edfff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libfontconfig.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/glibc-hwcaps/x86-64-v4/libfontconfig.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/glibc-hwcaps/x86-64-v4/", 0x7ffec5847dd0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/glibc-hwcaps/x86-64-v3/libfontconfig.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/glibc-hwcaps/x86-64-v3/", 0x7ffec5847dd0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/glibc-hwcaps/x86-64-v2/libfontconfig.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/glibc-hwcaps/x86-64-v2/", 0x7ffec5847dd0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/libfontconfig.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) newfstatat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/platforms/../../lib/", 0x7ffec5847dd0, 0) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=131979, ...}) = 0 mmap(NULL, 131979, PROT_READ, MAP_PRIVATE, 3, 0) = 0x7b39f3b73000 close(3) = 0 openat(AT_FDCWD, "/usr/lib/libfontconfig.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=321496, ...}) = 0 mmap(NULL, 324232, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f17b0000 mmap(0x7b39f17b6000, 196608, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39f17b6000 mmap(0x7b39f17e6000, 94208, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x36000) = 0x7b39f17e6000 mmap(0x7b39f17fd000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4c000) = 0x7b39f17fd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libfreetype.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libfreetype.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=821192, ...}) = 0 mmap(NULL, 823312, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39edb36000 mmap(0x7b39edb3c000, 606208, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39edb3c000 mmap(0x7b39edbd0000, 159744, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9a000) = 0x7b39edbd0000 mmap(0x7b39edbf7000, 36864, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc0000) = 0x7b39edbf7000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libQt5DBus.so.5", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0000Z\1\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=805248, ...}) = 0 mmap(NULL, 628408, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f0cc7000 mprotect(0x7b39f0cdb000, 536576, PROT_NONE) = 0 mmap(0x7b39f0cdb000, 434176, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14000) = 0x7b39f0cdb000 mmap(0x7b39f0d45000, 98304, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7e000) = 0x7b39f0d45000 mmap(0x7b39f0d5e000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x96000) = 0x7b39f0d5e000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libX11-xcb.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libX11-xcb.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=13976, ...}) = 0 mmap(NULL, 16400, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fae73000 mmap(0x7b39fae74000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fae74000 mmap(0x7b39fae75000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fae75000 mmap(0x7b39fae76000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fae76000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-icccm.so.4", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\260!\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=30704, ...}) = 0 mmap(NULL, 24800, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fae6c000 mmap(0x7b39fae6e000, 8192, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fae6e000 mmap(0x7b39fae70000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39fae70000 mmap(0x7b39fae71000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39fae71000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-image.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0@\22\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=23664, ...}) = 0 mmap(NULL, 20776, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fae66000 mmap(0x7b39fae67000, 8192, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fae67000 mmap(0x7b39fae69000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39fae69000 mmap(0x7b39fae6a000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39fae6a000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-shm.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\220\20\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=19352, ...}) = 0 mmap(NULL, 16488, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39fae61000 mmap(0x7b39fae62000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39fae62000 mmap(0x7b39fae63000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fae63000 mmap(0x7b39fae64000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39fae64000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-keysyms.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\320\20\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=18472, ...}) = 0 mmap(NULL, 16496, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9b26000 mmap(0x7b39f9b27000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39f9b27000 mmap(0x7b39f9b28000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f9b28000 mmap(0x7b39f9b29000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f9b29000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-randr.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0`r\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=93872, ...}) = 0 mmap(NULL, 69976, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1cf8000 mprotect(0x7b39f1cff000, 36864, PROT_NONE) = 0 mmap(0x7b39f1cff000, 20480, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f1cff000 mmap(0x7b39f1d04000, 12288, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b39f1d04000 mmap(0x7b39f1d08000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xf000) = 0x7b39f1d08000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-render-util.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0000\"\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=28680, ...}) = 0 mmap(NULL, 24952, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9b1f000 mmap(0x7b39f9b21000, 8192, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f9b21000 mmap(0x7b39f9b23000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39f9b23000 mmap(0x7b39f9b24000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39f9b24000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-render.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0000R\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=75168, ...}) = 0 mmap(NULL, 57656, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f3b64000 mprotect(0x7b39f3b69000, 32768, PROT_NONE) = 0 mmap(0x7b39f3b69000, 20480, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b39f3b69000 mmap(0x7b39f3b6e000, 8192, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa000) = 0x7b39f3b6e000 mmap(0x7b39f3b71000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b39f3b71000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-shape.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0p \0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=24136, ...}) = 0 mmap(NULL, 20568, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f9b19000 mmap(0x7b39f9b1b000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f9b1b000 mmap(0x7b39f9b1c000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f9b1c000 mmap(0x7b39f9b1d000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f9b1d000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-sync.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0 1\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=44640, ...}) = 0 mmap(NULL, 37048, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1cee000 mprotect(0x7b39f1cf1000, 20480, PROT_NONE) = 0 mmap(0x7b39f1cf1000, 12288, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f1cf1000 mmap(0x7b39f1cf4000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39f1cf4000 mmap(0x7b39f1cf6000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f1cf6000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-xfixes.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\2000\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=47384, ...}) = 0 mmap(NULL, 36968, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1ce4000 mprotect(0x7b39f1ce7000, 20480, PROT_NONE) = 0 mmap(0x7b39f1ce7000, 12288, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f1ce7000 mmap(0x7b39f1cea000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39f1cea000 mmap(0x7b39f1cec000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f1cec000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-xinerama.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0p\20\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=19432, ...}) = 0 mmap(NULL, 16472, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f3f0c000 mmap(0x7b39f3f0d000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39f3f0d000 mmap(0x7b39f3f0e000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f3f0e000 mmap(0x7b39f3f0f000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f3f0f000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-xkb.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0p\244\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=148896, ...}) = 0 mmap(NULL, 115288, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1793000 mmap(0x7b39f179d000, 49152, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa000) = 0x7b39f179d000 mmap(0x7b39f17a9000, 20480, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x16000) = 0x7b39f17a9000 mmap(0x7b39f17ae000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a000) = 0x7b39f17ae000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\20\307\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=218376, ...}) = 0 mmap(NULL, 169096, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f13d6000 mmap(0x7b39f13e2000, 77824, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b39f13e2000 mmap(0x7b39f13f5000, 36864, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1f000) = 0x7b39f13f5000 mmap(0x7b39f13fe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x27000) = 0x7b39f13fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libXext.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libXext.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=80952, ...}) = 0 mmap(NULL, 83776, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1ccf000 mmap(0x7b39f1cd3000, 45056, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39f1cd3000 mmap(0x7b39f1cde000, 16384, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xf000) = 0x7b39f1cde000 mmap(0x7b39f1ce2000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12000) = 0x7b39f1ce2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libX11.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libX11.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1309088, ...}) = 0 mmap(NULL, 1313000, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ed6bf000 mmap(0x7b39ed6d6000, 606208, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x17000) = 0x7b39ed6d6000 mmap(0x7b39ed76a000, 585728, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xab000) = 0x7b39ed76a000 mmap(0x7b39ed7f9000, 28672, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x139000) = 0x7b39ed7f9000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libSM.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libSM.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=38792, ...}) = 0 mmap(NULL, 36928, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1789000 mmap(0x7b39f178b000, 20480, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f178b000 mmap(0x7b39f1790000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f1790000 mmap(0x7b39f1791000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8000) = 0x7b39f1791000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libICE.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libICE.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=105304, ...}) = 0 mmap(NULL, 117944, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f176c000 mmap(0x7b39f1770000, 65536, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39f1770000 mmap(0x7b39f1780000, 16384, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14000) = 0x7b39f1780000 mmap(0x7b39f1784000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x18000) = 0x7b39f1784000 mmap(0x7b39f1786000, 11448, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39f1786000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxkbcommon-x11.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\3605\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=45872, ...}) = 0 mmap(NULL, 37632, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f13cc000 mmap(0x7b39f13cf000, 12288, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f13cf000 mmap(0x7b39f13d2000, 8192, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39f13d2000 mmap(0x7b39f13d4000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f13d4000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxkbcommon.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\20U\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=295888, ...}) = 0 mmap(NULL, 266896, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f06be000 mprotect(0x7b39f06c3000, 237568, PROT_NONE) = 0 mmap(0x7b39f06c3000, 110592, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b39f06c3000 mmap(0x7b39f06de000, 122880, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x20000) = 0x7b39f06de000 mmap(0x7b39f06fd000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3e000) = 0x7b39f06fd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxml2.so.2", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libxml2.so.2", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1358936, ...}) = 0 mmap(NULL, 1361032, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39eb0b3000 mmap(0x7b39eb0d4000, 933888, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x21000) = 0x7b39eb0d4000 mmap(0x7b39eb1b8000, 241664, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x105000) = 0x7b39eb1b8000 mmap(0x7b39eb1f3000, 49152, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x140000) = 0x7b39eb1f3000 mmap(0x7b39eb1ff000, 1160, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39eb1ff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libbz2.so.1.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libbz2.so.1.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=74720, ...}) = 0 mmap(NULL, 76840, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f13b9000 mmap(0x7b39f13bb000, 53248, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f13bb000 mmap(0x7b39f13c8000, 8192, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xf000) = 0x7b39f13c8000 mmap(0x7b39f13ca000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x10000) = 0x7b39f13ca000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libpng16.so.16", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libpng16.so.16", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=239640, ...}) = 0 mmap(NULL, 237584, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ef6c5000 mmap(0x7b39ef6cb000, 172032, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x6000) = 0x7b39ef6cb000 mmap(0x7b39ef6f5000, 36864, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x30000) = 0x7b39ef6f5000 mmap(0x7b39ef6fe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x39000) = 0x7b39ef6fe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libharfbuzz.so.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libharfbuzz.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1183648, ...}) = 0 mmap(NULL, 1186536, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ea6de000 mmap(0x7b39ea6ea000, 909312, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b39ea6ea000 mmap(0x7b39ea7c8000, 217088, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xea000) = 0x7b39ea7c8000 mmap(0x7b39ea7fd000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x11e000) = 0x7b39ea7fd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libbrotlidec.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libbrotlidec.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=55168, ...}) = 0 mmap(NULL, 57360, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f13aa000 mmap(0x7b39f13ab000, 36864, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39f13ab000 mmap(0x7b39f13b4000, 12288, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xa000) = 0x7b39f13b4000 mmap(0x7b39f13b7000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xc000) = 0x7b39f13b7000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdbus-1.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libdbus-1.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libdbus-1.so.3", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=334008, ...}) = 0 mmap(NULL, 336624, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39ede72000 mmap(0x7b39ede80000, 200704, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe000) = 0x7b39ede80000 mmap(0x7b39edeb1000, 69632, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3f000) = 0x7b39edeb1000 mmap(0x7b39edec2000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4f000) = 0x7b39edec2000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libxcb-util.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0002\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0555, st_size=32584, ...}) = 0 mmap(NULL, 28936, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f20a8000 mprotect(0x7b39f20ab000, 12288, PROT_NONE) = 0 mmap(0x7b39f20ab000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f20ab000 mmap(0x7b39f20ac000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39f20ac000 mmap(0x7b39f20ae000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b39f20ae000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libXau.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libXau.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=14232, ...}) = 0 mmap(NULL, 16424, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1cca000 mmap(0x7b39f1ccb000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39f1ccb000 mmap(0x7b39f1ccc000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f1ccc000 mmap(0x7b39f1ccd000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f1ccd000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libXdmcp.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libXdmcp.so.6", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=26488, ...}) = 0 mmap(NULL, 28688, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f13a2000 mmap(0x7b39f13a4000, 8192, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f13a4000 mmap(0x7b39f13a6000, 8192, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x4000) = 0x7b39f13a6000 mmap(0x7b39f13a8000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x5000) = 0x7b39f13a8000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libuuid.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libuuid.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=34936, ...}) = 0 mmap(NULL, 36936, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f1398000 mmap(0x7b39f139a000, 20480, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f139a000 mmap(0x7b39f139f000, 4096, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f139f000 mmap(0x7b39f13a0000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x7000) = 0x7b39f13a0000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libicuuc.so.75", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libicuuc.so.75", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=2070576, ...}) = 0 mmap(NULL, 2077600, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39e6a04000 mmap(0x7b39e6a4b000, 1130496, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x47000) = 0x7b39e6a4b000 mmap(0x7b39e6b5f000, 569344, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x15b000) = 0x7b39e6b5f000 mmap(0x7b39e6bea000, 81920, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1e6000) = 0x7b39e6bea000 mmap(0x7b39e6bfe000, 5024, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39e6bfe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libgraphite2.so.3", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libgraphite2.so.3", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=133064, ...}) = 0 mmap(NULL, 135184, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f069c000 mmap(0x7b39f069e000, 98304, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39f069e000 mmap(0x7b39f06b6000, 20480, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1a000) = 0x7b39f06b6000 mmap(0x7b39f06bb000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1e000) = 0x7b39f06bb000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libbrotlicommon.so.1", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libbrotlicommon.so.1", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=141264, ...}) = 0 mmap(NULL, 139280, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39eeedd000 mmap(0x7b39eeede000, 4096, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1000) = 0x7b39eeede000 mmap(0x7b39eeedf000, 126976, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0x7b39eeedf000 mmap(0x7b39eeefe000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x21000) = 0x7b39eeefe000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libsystemd.so.0", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libsystemd.so.0", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=1185128, ...}) = 0 mmap(NULL, 1190152, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39e9add000 mmap(0x7b39e9af1000, 786432, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x14000) = 0x7b39e9af1000 mmap(0x7b39e9bb1000, 262144, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xd4000) = 0x7b39e9bb1000 mmap(0x7b39e9bf1000, 57344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x113000) = 0x7b39e9bf1000 mmap(0x7b39e9bff000, 2312, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7b39e9bff000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libicudata.so.75", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libicudata.so.75", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\0\0\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=30737240, ...}) = 0 mmap(NULL, 30740480, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39e4c00000 mmap(0x7b39e6950000, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x1d4f000) = 0x7b39e6950000 close(3) = 0 openat(AT_FDCWD, "/opt/intelFPGA/23.1/quartus/linux64/libcap.so.2", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory) openat(AT_FDCWD, "/usr/lib/libcap.so.2", O_RDONLY|O_CLOEXEC) = 3 read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0 |\0\0\0\0\0\0"..., 832) = 832 fstat(3, {st_mode=S_IFREG|0755, st_size=43064, ...}) = 0 mmap(NULL, 45128, PROT_READ, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7b39f0cbb000 mmap(0x7b39f0cbe000, 20480, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x3000) = 0x7b39f0cbe000 mmap(0x7b39f0cc3000, 8192, PROT_READ, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x8000) = 0x7b39f0cc3000 mmap(0x7b39f0cc5000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x9000) = 0x7b39f0cc5000 close(3) = 0 munmap(0x7b39f3b73000, 131979) = 0 munmap(0x7b39fae78000, 20544) = 0 munmap(0x7b39edec5000, 1288232) = 0 munmap(0x7b39f17b0000, 324232) = 0 munmap(0x7b39f0cc7000, 628408) = 0 munmap(0x7b39fae73000, 16400) = 0 munmap(0x7b39fae6c000, 24800) = 0 munmap(0x7b39fae66000, 20776) = 0 munmap(0x7b39fae61000, 16488) = 0 munmap(0x7b39f9b26000, 16496) = 0 munmap(0x7b39f1cf8000, 69976) = 0 munmap(0x7b39f9b1f000, 24952) = 0 munmap(0x7b39f3b64000, 57656) = 0 munmap(0x7b39f9b19000, 20568) = 0 munmap(0x7b39f1cee000, 37048) = 0 munmap(0x7b39f1ce4000, 36968) = 0 munmap(0x7b39f3f0c000, 16472) = 0 munmap(0x7b39f1ccf000, 83776) = 0 munmap(0x7b39ed6bf000, 1313000) = 0 munmap(0x7b39f1789000, 36928) = 0 munmap(0x7b39f176c000, 117944) = 0 munmap(0x7b39f13cc000, 37632) = 0 munmap(0x7b39f1793000, 115288) = 0 munmap(0x7b39f06be000, 266896) = 0 munmap(0x7b39eb0b3000, 1361032) = 0 munmap(0x7b39ea6de000, 1186536) = 0 munmap(0x7b39edb36000, 823312) = 0 munmap(0x7b39ef6c5000, 237584) = 0 munmap(0x7b39f13b9000, 76840) = 0 munmap(0x7b39f13aa000, 57360) = 0 munmap(0x7b39ede72000, 336624) = 0 munmap(0x7b39f20a8000, 28936) = 0 munmap(0x7b39f13d6000, 169096) = 0 munmap(0x7b39f1cca000, 16424) = 0 munmap(0x7b39f13a2000, 28688) = 0 munmap(0x7b39f1398000, 36936) = 0 munmap(0x7b39e6a04000, 2077600) = 0 munmap(0x7b39f069c000, 135184) = 0 munmap(0x7b39eeedd000, 139280) = 0 munmap(0x7b39e9add000, 1190152) = 0 munmap(0x7b39e4c00000, 30740480) = 0 munmap(0x7b39f0cbb000, 45128) = 0 access("/opt/intelFPGA/23.1/quartus/linux64/platforms/libqxcb.so", F_OK) = 0 rt_sigprocmask(SIG_UNBLOCK, [ABRT], NULL, 8) = 0 gettid() = 375096 getpid() = 375096 tgkill(375096, 375096, SIGABRT) = 0 --- SIGABRT {si_signo=SIGABRT, si_code=SI_TKILL, si_pid=375096, si_uid=1000} --- +++ killed by SIGABRT (core dumped) +++