Model> vsim work.tb_jesd -L soc_system -L core_pllV2 -L altera_lnsim # vsim work.tb_jesd -L soc_system -L core_pllV2 -L altera_lnsim # Start time: 09:40:04 on Jun 17,2021 # Loading work.tb_jesd # Loading soc_system.soc_system_system_0 # Loading soc_system.soc_system_system_0_jesd204b # ** Error: (vsim-3033) G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b.v(699): Instantiation of 'altera_jesd204_rx_base' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /tb_jesd/soc_system_system_0_DUT/jesd204b File: G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b.v # Searched libraries: # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/soc_system # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/core_pllV2 # C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/rtl_work # ** Error: (vsim-3033) G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b.v(799): Instantiation of 'altera_jesd204_tx_base' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /tb_jesd/soc_system_system_0_DUT/jesd204b File: G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b.v # Searched libraries: # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/soc_system # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/core_pllV2 # C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/rtl_work # Loading soc_system.soc_system_system_0_jesd204b_inst_phy # ** Error: (vsim-3033) G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b_inst_phy.v(205): Instantiation of 'altera_jesd204_tx_mlpcs' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /tb_jesd/soc_system_system_0_DUT/jesd204b/inst_phy File: G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b_inst_phy.v # Searched libraries: # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/soc_system # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/core_pllV2 # C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/rtl_work # ** Error: (vsim-3033) G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b_inst_phy.v(229): Instantiation of 'altera_jesd204_rx_mlpcs' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /tb_jesd/soc_system_system_0_DUT/jesd204b/inst_phy File: G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b_inst_phy.v # Searched libraries: # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/soc_system # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/core_pllV2 # C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/rtl_work # ** Error: (vsim-3033) G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b_inst_phy.v(264): Instantiation of 'altera_jesd204_phy_adapter' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /tb_jesd/soc_system_system_0_DUT/jesd204b/inst_phy File: G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/soc_system/synthesis/submodules/soc_system_system_0_jesd204b_inst_phy.v # Searched libraries: # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/soc_system # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/core_pllV2 # C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim # G:/ROMAN/SYSCONHF/Prototypes/DebugKit/GHRD_SocKit_AN755_DebugKit/simulation/modelsim/rtl_work # Loading sv_std.std # Loading soc_system.altera_xcvr_functions # Loading soc_system.altera_xcvr_native_av_functions_h # Loading soc_system.altera_xcvr_native_av_sv_unit # Loading soc_system.altera_xcvr_native_av # Loading soc_system.sv_reconfig_bundle_merger_sv_unit # Loading soc_system.sv_reconfig_bundle_merger # Loading soc_system.altera_avalon_mm_bridge # Loading soc_system.altera_reset_sequencer # Loading soc_system.altera_reset_controller # Loading soc_system.altera_reset_sequencer_deglitch_main # Loading soc_system.altera_reset_sequencer_main # Loading soc_system.altera_reset_sequencer_seq # Loading soc_system.altera_reset_sequencer_dlycntr # Loading soc_system.alt_xcvr_reconfig_h # Loading soc_system.alt_xcvr_reconfig # Loading soc_system.alt_xcvr_resync # Loading soc_system.alt_xcvr_arbiter # Loading soc_system.alt_xcvr_reconfig_cal_seq # Loading soc_system.alt_xcvr_reconfig_basic # Loading soc_system.altera_xcvr_reset_control # Loading soc_system.soc_system_system_0_mm_interconnect_0 # Loading soc_system.altera_merlin_master_translator # Loading soc_system.altera_merlin_slave_translator # Loading soc_system.altera_merlin_master_agent # Loading soc_system.altera_merlin_slave_agent # Loading soc_system.altera_merlin_burst_uncompressor # Loading soc_system.altera_avalon_sc_fifo # Loading soc_system.soc_system_system_0_mm_interconnect_0_router # Loading soc_system.soc_system_system_0_mm_interconnect_0_router_default_decode # Loading soc_system.soc_system_system_0_mm_interconnect_0_router_001 # Loading soc_system.soc_system_system_0_mm_interconnect_0_router_001_default_decode # Loading soc_system.altera_merlin_traffic_limiter # Loading soc_system.altera_merlin_burst_adapter # Loading soc_system.soc_system_system_0_mm_interconnect_0_cmd_demux # Loading soc_system.soc_system_system_0_mm_interconnect_0_cmd_mux # Loading soc_system.soc_system_system_0_mm_interconnect_0_rsp_demux # Loading soc_system.soc_system_system_0_mm_interconnect_0_rsp_mux # Loading soc_system.altera_merlin_arbitrator # Loading soc_system.altera_merlin_arb_adder # Loading soc_system.soc_system_mm_interconnect_4_avalon_st_adapter_001 # Loading soc_system.soc_system_mm_interconnect_4_avalon_st_adapter_001_error_adapter_0 # Loading core_pllV2.core_pllV2_0002 # Loading altera_lnsim.altera_lnsim_functions # Loading altera_lnsim.altera_pll # Loading work.pattern_generator_top # Loading work.alternate_generator # Loading work.ramp_generator # Loading work.prbs_generator # Loading work.altera_jesd204_transport_tx_top # Loading work.altera_jesd204_assembler # Loading work.altera_jesd204_deassembler # Error loading design # End time: 09:40:05 on Jun 17,2021, Elapsed time: 0:00:01 # Errors: 5, Warnings: 0